Datasheet > DAC1627D1G25HN/C1,

DAC1627D1G25HN/C1,

更新时间： 2024-11-05 14:41:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
81页	508K
描述
Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating, SOT813-3 Package, Standard Markigg, Reel Dry Pack, SMD, 13"

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DAC1627D1G25HN/C1, 技术参数

Source Url Status Check Date：	2012-06-13 00:00:00	是否Rohs认证：	符合
生命周期：	Preview	Reach Compliance Code：	unknown
风险等级：	5.57	Is Samacsys：	N
Base Number Matches：	1

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DAC1627D1G25

Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and

x8 interpolating

Rev. 4.00 — 12 December 2012

Product data sheet

1. General description

The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter

(DAC). It incorporates selectable ×2, ×4 and ×8 interpolation filters optimized for

multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 Gsps. The

DAC1627D1G25 is supplied by two power supplies and integrates a differential scalable

output current up to 34 mA.

The DAC1627D1G25 meets multi-carrier Global System for Mobile communications

(GSM) specifications. For example, with an NCO frequency of 153.6 MHz and a DAC

clock frequency of 1.2288 Gsps the full-scale dynamic range is:

•

SFDR_RBW= 90 dBc (bandwidth = 180 MHz)

IMD3 = 85 dBc

The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.

The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data

Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR

interface accepts a multiplex input data stream such as interleaved or folded. An internal

LVDS input auto-calibration ensures the robustness and stability of the interface.

Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A

40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution

internal gain, phase and offset control provide outstanding image and Local Oscillator

(LO) signal rejection at the system analog modulator output.

An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at

the DAC output.

Multiple Device Synchronization (MDS) allows synchronization of the outputs of multiple

DAC devices. MDS guarantees a maximum skew of one output clock period between

several devices.

The DAC1627D1G25 includes a low noise capacitor-free integrated Phase-Locked Loop

(PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.

The DAC1627D1G25 is available in an HVQFN72 package (10 mm × 10 mm).

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与DAC1627D1G25HN/C1,相关器件

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DAC1653D1G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653D1G5NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
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DAC1653Q	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G0NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G25NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G5NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1658D1G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1658D1G5NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH

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