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DAC1653D2G0NLGA PDF预览

DAC1653D2G0NLGA

更新时间: 2024-11-05 21:03:23
品牌 Logo 应用领域
艾迪悌 - IDT 转换器
页数 文件大小 规格书
168页 3777K
描述
D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, VFQFP-56

DAC1653D2G0NLGA 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:VFQFP-56Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.71最大模拟输出电压:1 V
最小模拟输出电压:转换器类型:D/A CONVERTER
输入位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输入格式:SERIAL
JESD-30 代码:S-XQCC-N56长度:8 mm
位数:16功能数量:1
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:0.9 mm标称安定时间 (tstl):0.02 µs
标称供电电压:1.2 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

DAC1653D2G0NLGA 数据手册

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DAC1653D/DAC1658D  
®
Dual 16-bit DAC: 10 Gbps JESD204B interface:  
x2, x4 and x8 interpolating  
Datasheet  
Revision 2.41  
1. GENERAL DESCRIPTION  
DAC1653D and DAC1658D are high-speed, high-performance 16-bit dual channel Digital-to-Analog Converters (DACs).  
The devices provide sample rates up to 2 Gsps with selectable 2, 4 and 8 interpolation filters optimized for multi-carrier  
and broadband wireless transmitters.  
When both devices are referred to in this data sheet, the following convention will be used: DAC165xD.  
The DAC165xD integrates a JEDEC JESD204B compatible high-speed serial input data interface running up to 10 Gbps  
allowing dual channel input sampling at up to 1 Gsps over four differential lanes. It offers numerous advantages over  
traditional parallel digital interfaces:  
Easier Printed-Circuit Board (PCB) layout  
Lower radiated noise  
Lower pin count  
Self-synchronous link  
Skew compensation  
Deterministic latency  
Multiple Device Synchronization (MDS); JESD204B subclass 1 compatible  
Harmonic clocking support  
Assured FPGA interoperability  
There are two versions of the DAC165xD:  
Low common-mode output voltage (part identification DAC1653D)  
High common-mode output voltage (part identification DAC1658D)  
An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by  
writing to the Serial Peripheral Interface (SPI) control registers associated with the on-chip 40-bit Numerically Controlled  
Oscillator (NCO). This accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment feature, the  
12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals.  
The DAC165xD is fully compatible with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic  
and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to  
reduce system-level clock synthesis and distribution challenges.  
Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample synchronous and phase coherent to  
within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications.  
The DAC165xD includes a 2, 4 or 8 divider to achieve the best possible noise performance at the analog outputs,  
allowing harmonic clocking through the system. The internal regulator adjusts the full-scale output current between 10 mA  
and 30 mA.  
The device is available in a VFQFP-N 56 package (8 mm 8 mm).  
2013, Integrated Device Technology, Inc. (IDT) and its subsidiaries reserves the right to change the detail specifications as may be required to permit improvements in the design of its product.  

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