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DAC1653Q1G0NAGA PDF预览

DAC1653Q1G0NAGA

更新时间: 2024-09-16 12:26:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
101页 5697K
描述
Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50

DAC1653Q1G0NAGA 数据手册

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DAC1653Q/DAC1658Q  
Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50  
Gsps; x2, x4 and x8 interpolating  
Rev. 1.03 — 13 May 2013  
Advance data sheet  
1. General description  
The DAC1658Q and the DAC1653Q are high-speed high-performance 16-bit quad  
channel digital-to-analog converter (DAC) with high and low common-mode output. The  
devices provide a sample rate up to 1.50 Gsps with selectable ,  and  interpolation  
filters optimized for multi-carrier and broadband wireless transmitters.  
When both devices are referred to in this data sheet, the following convention will be  
used: DAC165xQ.  
The DAC165xQ integrates a JESD204B high-speed serial input data interface running up  
to 10 Gbps allowing quad channel input sampling at up to 750 Msps over eight differential  
lanes. It offers numerous advantages over traditional parallel digital interfaces:  
Easier Printed-Circuit Board (PCB) layout  
Lower radiated noise  
Lower pin count  
Self-synchronous link  
Skew compensation  
Deterministic latency  
Multiple Device Synchronization (MDS); JESD204B subclass 1 support  
Harmonic clocking support  
Assured FPGA interoperability  
There are two versions of the DAC165xQ:  
Low common-mode output voltage (part identification DAC1653Q)  
High common-mode output voltage (part identification DAC1658Q)  
Two optional on-chip digital modulators convert the complex I/Q pattern from baseband to  
IF. The mixer frequency is set by writing to the Serial Peripheral Interface (SPI) control  
registers associated with the on-chip 40-bit Numerically Controlled Oscillator (NCO). This  
accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment  
feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog  
output signals.  
The DAC165xQ is fully compatible with device subclass 1 of the JEDEC JESD204B  
standard, guaranteeing deterministic and repeatable interface latency using the  
differential SYSREF signal. The device also supports harmonic clocking to reduce  
system-level clock synthesis and distribution challenges.  
The Advance Information presented herein represents a product that is developmental or prototype. The noted characteristics are design targets. Integrated Device Technologies, Inc. (IDT)  
reserves the right to change any circuitry or specifications without notice.  
®

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