Datasheet > DAC1628D1G25HN

DAC1628D1G25HN

更新时间： 2024-11-05 21:19:27

品牌	Logo	应用领域
艾迪悌 - IDT		转换器
页数	文件大小	规格书
130页	2361K
描述
D/A Converter, 2 Func, PQCC56

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技术参数
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DAC1628D1G25HN 技术参数

生命周期：	Obsolete	包装说明：	QCCN, LCC56,.31SQ,20
Reach Compliance Code：	compliant	风险等级：	5.84
转换器类型：	D/A CONVERTER	输入位码：	BINARY, 2'S COMPLEMENT BINARY
JESD-30 代码：	S-PQCC-N56	位数：	16
功能数量：	2	端子数量：	56
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC56,.31SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	1.8,1.8/3.3 V
认证状态：	Not Qualified	子类别：	Other Converters
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

DAC1628D1G25HN 数据手册

DAC1628D1G25

Dual 16-bit DAC: JESD204B interface: up to 1.25 Gsps; x2, x4

and x8 interpolating

Rev. 02 — 2 July 2012

Objective data sheet

1. General description

The DAC1628D1G25 is a high-speed high-performance 16-bit dual channel

digital-to-analog converter (DAC). The device provides a sample rate up to 1.25 Gsps with

selectable 2, 4 and 8 interpolation filters optimized for multi-carrier and broadband

wireless transmitters.

The DAC1628D1G25 integrates a CVGxpress high-speed serial input data interface

running up to 6.25 Gbps allowing dual channel input sampling at up to 625 Msps over four

differential lanes. CGVXpress is fully compliant with the JEDEC JESD204B standard. It

offers numerous advantages over traditional parallel digital interfaces:

• Easier Printed-Circuit Board (PCB) layout

• Lower radiated noise

• Lower pin count

• Self-synchronous link

• Skew compensation

• Deterministic latency

• Multiple Device Synchronization (MDS)

• Harmonic clocking support

• Assured FPGA interoperability

An optional on-chip digital modulation converts the complex I/Q pattern from baseband to

IF. The mixer frequency is set by writing to the Serial Peripheral Interface (SPI) control

registers associated with the on-chip 40-bit Numerically Controlled Oscillator (NCO). This

accurately places the IF carrier in the frequency domain. The 16-bit phase adjustment

feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog

output signals.

The DAC1628D1G25 is fully compliant with device subclass 1 of the JEDEC JESD204B

standard, guaranteeing deterministic and repeatable interface latency using the

differential SYSREF signal. The device also supports harmonic clocking to reduce

system-level clock synthesis and distribution challenges.

Multiple Device Synchronization (MDS, a unique CGVxpress feature) enables up to

16 DAC channels to be sample synchronous and phase coherent to within one DAC clock

period. MDS is ideal for LTE and LTE-A MIMO transceiver applications.

12 3 4 5 6 7...130

中文翻译

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与DAC1628D1G25HN相关器件

型号	品牌	获取价格	描述	数据表
DAC1653D1G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653D1G5NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653D2G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653Q	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G0NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G25NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G5NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1658D1G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1658D1G5NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1658D2G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH

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