CYW305OXC

更新时间： 2024-02-23 17:31:44

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		晶体外围集成电路光电二极管控制器时钟
页数	文件大小	规格书
21页	247K
描述
Frequency Controller with System Recovery for Intel Integrated Core Logic

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数据手册

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CYW305OXC 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	56
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.26
JESD-30 代码：	R-PDSO-G56	长度：	18.415 mm
端子数量：	56	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率：	14.31818 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.5057 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

CYW305OXC 数据手册

W305B

0 ns

10 ns

20 ns

30 ns

40 ns

Cycle Repeat

CPU 133-MHz

SDRAM 133MHz

3V66 66-MHz

PCI 33-MHz

APIC 16.6-MHz

REF 14.318-MHz

USB 48-MHz

DOT 48-MHz

Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM)

Serial Data Interface

The W305B features a two-pin, serial data interface that can

be used to configure internal register settings that control

particular device functions.

controller. For block write/read operation, the bytes must be

accessed in sequential order from lowest to highest byte with

the ability to stop after any complete byte has been trans-

ferred. For byte/word write and byte read operations, system

controller can access individual indexed byte. The offset of the

indexed byte is encoded in the command code.

Data Protocol

The definition for the command code is given in Table 1.

The clock driver serial protocol supports byte/word write,

byte/word read, block write and block read operations from the

Table 1. Command Code Definition

Bit

Descriptions

0 = Block read or block write operation

1 = Byte/Word read or byte/word write operation

6:0

Byte offset for byte/word read or write operation. For block read or write operations, these bits

need to be set at ‘0000000’.

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

Description

Bit

Start

2:8

Slave address – 7 bit

Write

2:8

Slave address – 7 bit

Write

Acknowledge from slave

11:18

Command Code – 8 bit

11:18

Command Code – 8 bit

‘00000000’ stands for block operation

20:27

29:36

38:45

...

Acknowledge from slave

Byte Count – 8 bits

Acknowledge from slave

Data byte 0 – 8 bits

Acknowledge from slave

Data byte 1 – 8 bits

Acknowledge from slave

Data Byte N/Slave Acknowledge...

21:27

30:37

Acknowledge from slave

Repeat start

Slave address – 7 bits

Read

Acknowledge from slave

Byte count from slave – 8 bits

Acknowledge

39:46

Data byte from slave – 8 bits

Document #: 38-07262 Rev. *B

Page 5 of 21

1 2 3 456 7 8...21

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与CYW305OXC相关器件

型号	品牌	描述	获取价格	数据表
CYW305OXCT	CYPRESS	Frequency Controller with System Recovery for Intel Integrated Core Logic	获取价格
CYW305OXCT	SPECTRALINEAR	Frequency Controller with System Recovery for Intel Integrated Core Logic	获取价格
CYW311OXC	CYPRESS	FTG for VIA⑩ Pro-266 DDR Chipset	获取价格
CYW311OXC	SPECTRALINEAR	FTG for VIA⑩ Pro-266 DDR Chipset	获取价格
CYW311OXCT	CYPRESS	FTG for VIA⑩ Pro-266 DDR Chipset	获取价格
CYW311OXCT	SPECTRALINEAR	FTG for VIA⑩ Pro-266 DDR Chipset	获取价格

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