CYW305OXC

更新时间： 2024-02-19 05:26:05

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		晶体外围集成电路光电二极管控制器时钟
页数	文件大小	规格书
21页	247K
描述
Frequency Controller with System Recovery for Intel Integrated Core Logic

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技术参数
数据手册

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CYW305OXC 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	56
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.26
JESD-30 代码：	R-PDSO-G56	长度：	18.415 mm
端子数量：	56	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率：	14.31818 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.5057 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

CYW305OXC 数据手册

W305B

Output Strapping Resistor

Series Termination Resistor

Clock Load

W305B

Output

Buffer

Power-on

Reset

Hold

Output Three-state

10 kΩ

Output

Low

Timer

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

After 2 ms, the pin becomes an output. Assuming the power

supply has stabilized by then, the specified output frequency

is delivered on the pins. If the power supply has not yet

reached full value, output frequency initially may be below

target but will increase to target once supply voltage has stabi-

lized. In either case, a short output clock cycle may be

produced from the CPU clock outputs when the outputs are

enabled.

Overview

The W305B is a highly integrated frequency timing generator,

supplying all the required clock sources for an Intel^®archi-

tecture platform using graphics integrated core logic.

Functional Description

I/O Pin Operation

Upon power-up the power on strap option pins act as a logic

input. An external 10-kΩ strapping resistor should be used.

Figure 1 shows a suggested method for strapping resistor

connections.

Offsets Among Clock Signal Groups

Figure 2, Figure 3, and Figure 4 represent the phase

relationship among the different groups of clock outputs from

W305B under different frequency modes.

10 ns

20 ns

30 ns

40 ns

0 ns

CPU 66 Period

CPU 66-MHz

SDRAM 100 Period

SDRAM 100-MHz

Hub-PCI

3V66 66-MHz

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz

APIC 16.6-MHz

Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)

Document #: 38-07262 Rev. *B

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