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CYRF69313-40LFXC PDF预览

CYRF69313-40LFXC

更新时间: 2024-11-21 12:27:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器和处理器外围集成电路uCs集成电路uPs集成电路无线
页数 文件大小 规格书
81页 810K
描述
Programmable Radio-on-Chip LPstar

CYRF69313-40LFXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC40,.24SQ,20
针数:40Reach Compliance Code:unknown
ECCN代码:5A991.B.1HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.81
Is Samacsys:NJESD-30 代码:S-XQCC-N40
长度:6 mm端子数量:40
最高工作温度:70 °C最低工作温度:
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源:3.3,5 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Other Microprocessor ICs最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:6 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CYRF69313-40LFXC 数据手册

 浏览型号CYRF69313-40LFXC的Datasheet PDF文件第2页浏览型号CYRF69313-40LFXC的Datasheet PDF文件第3页浏览型号CYRF69313-40LFXC的Datasheet PDF文件第4页浏览型号CYRF69313-40LFXC的Datasheet PDF文件第5页浏览型号CYRF69313-40LFXC的Datasheet PDF文件第6页浏览型号CYRF69313-40LFXC的Datasheet PDF文件第7页 
CYRF69313  
Programmable Radio-on-Chip LPstar  
Programmable Radio-on-Chip LPstar  
Simple Development  
Features  
Auto transaction sequencer (ATS): MCU can stay sleeping  
longer to save power  
Radio System-on-Chip, with built-in 8-bit MCU in a single  
device.  
Framing, length, CRC16, and Auto ACK  
Separate 16 byte transmit and receive FIFOs  
Receive signal strength indication (RSSI)  
Operates in the unlicensed worldwide Industrial, Scientific, and  
Medical (ISM) band (2.400 GHz to 2.483 GHz).  
On Air compatible with second generation radio  
WirelessUSB™ LP and PRoC LP.  
Built-in serial peripheral interface (SPI) control while in sleep  
mode  
Pin-to-pin compatible with PRoC LP except the pin 31 and  
pin 37.  
AdvanceddevelopmenttoolsbasedonCypress’sPSoC® Tools  
Intelligent  
Flexible I/O  
M8C based 8-bit CPU, optimized for human interface devices  
(HID) applications  
2 mA source current on all GPIO pins. Configurable 8 mA or  
50 mA/pin current sink on designated pins  
256 bytes of SRAM  
Each GPIO pin supports high impedance inputs, configurable  
pull-up, open-drain output, CMOS/TTL inputs, and CMOS  
output  
8 Kbytes of flash memory with EEPROM emulation  
In-System reprogrammable through D+/D– pins  
CPU speed up to 12 MHz  
Maskable interrupts on all I/O pins  
BOM Savings  
16-bit free running timer  
Low external component count  
Small footprint 40-pin QFN (6 mm × 6 mm)  
GPIOs that require no external components  
Operates off a single crystal  
Integrated 3.3 V regulator  
Low power wakeup timer  
12-bit programmable interval timer with interrupts  
Watchdog timer  
Low Power  
21 mA operating current (Transmit at –5 dBm)  
Sleep current less than 1 µA  
Integrated pull-up on D–  
USB Specification Compliance  
Operating voltage from 4.0 V to 5.25 V DC  
Fast startup and fast channel changes  
Supports coin-cell operated applications  
Conforms to USB specification version 2.0  
Conforms to USB HID specification version 1.1  
Supports one low speed USB device address  
Supports one control endpoint and two data end points  
Integrated USB transceiver  
Reliable and Robust  
Receive sensitivity typical –90 dBm  
AutoRate™ – dynamic data rate reception  
Applications  
Enables data reception for any of the supported bit rates  
automatically.  
Wireless keyboards and mice  
Presentation tools  
Wireless gamepads  
Remote controls  
Toys  
DSSS (250 Kbps), GFSK (1 Mbps)  
Operating temperature from 0 °C to 70 °C  
Closed-loop frequency synthesis for minimal frequency drift  
Fitness  
Cypress Semiconductor Corporation  
Document Number: 001-66503 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 27, 2013  

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