CYRS1543AV18
CYRS1545AV18
72-Mbit QDR® II+ SRAM Four-Word Burst
Architecture with RadStop™ Technology
72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology
■ Available in 165-ball CCGA (21 ×25 ×2.83 mm)
■ HSTL inputs and variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ DLL for accurate data placement
Radiation Performance
Radiation Data
■ Total Dose =300 Krad
■ Soft error rate (both Heavy Ion and proton)
Heavy ions 1 × 10-10 upsets/bit-day with single error
correction - double error detection error detection and
correction (SEC-DED EDAC)
Configurations
CYRS1543AV18 – 4 M × 18
■ Neutrons = 2.0 × 1014 N/cm2
CYRS1545AV18 – 2 M × 36
■ Dose rate = 2.0 × 109 rad(Si)/sec
Functional Description
■ Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 (rad(Si)/sec
■ Latch up immunity = 120 MeV.cm2/mg (125 °C)
The CYRS1543AV18 and CYRS1545AV18 are synchronous
pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with
RadStop™ technology. Cypress’s state-of-the-art RadStop
Technology is radiation hardened through proprietary design and
process hardening techniques.
Prototyping
■ Non-qualified CYPT1543AV18, and CYPT1545AV18 devices
with same functional and timing characteristics in a
165-ball Ceramic Column Grid Array (CCGA) package
The QDR II+ architecture consists of two separate ports: the read
port and the write port to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
QDR II+ architecture has separate data inputs and data outputs
to completely eliminate the need to turnaround the data bus that
exists with common I/O devices. Each port can be accessed
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CYRS1543AV18) or 36-bit words (CYRS1545AV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus turnarounds.
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 250 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports
at 250 MHz (data transferred at 500 MHz)
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Single multiplexed address input bus latches address inputs
for read and write ports
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II+ operates with 2.0 cycle read latency when the delay
lock loop (DLL) is enabled
Selection Guide
Description
250 MHz Unit
■ Available in × 18, and × 36 configurations
Maximum operating frequency
250
1225
1225
MHz
mA
■ Full data coherency, providing most current data
■ Core VDD = 1.8 (± 0.1 V); I/O VDDQ = 1.4 V to VDD
Maximum operating current (125C, × 18
concurrent R/W)
× 36
Cypress Semiconductor Corporation
Document Number: 001-60007 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 4, 2013
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