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CYRF89435 PDF预览

CYRF89435

更新时间: 2024-11-21 12:51:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
40页 598K
描述
PRoC™ - CapSense®

CYRF89435 数据手册

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CYRF89435  
PRoC™ - CapSense®  
PRoC™ - CapSense®  
Precision, programmable clocking  
Internal main oscillator (IMO): 6/12/24 MHz ± 5%  
Internal low-speed oscillator (ILO) at 32 kHz for watchdog  
and sleep timers  
PRoC-CS Features  
Single Device, Two functions  
8-bit flash based capacitive touch controller MCU function  
and 2.4-GHz WirelessUSB™ NL radio transceiver function  
in a single device  
Precision 32 kHz oscillator for optional external crystal  
Programmable pin configurations  
Wide operating range: 1.9 V to 3.6 V  
Configurable capacitive sensing elements  
7 μA per sensor at 500 ms scan rate  
Supports SmartSense™ Auto-tuning  
Up to 13 general-purpose I/Os (GPIOs)  
Dual mode GPIO: All GPIOs support digital I/O and analog  
inputs  
25-mA sink current on each GPIO  
• 120 mA total sink current on all GPIOs  
Pull-up, high Z, open-drain modes on all GPIOs  
CMOS drive mode –5 mA source current on ports 0 and 1  
and 1 mA on port 2  
20 mA total source current on all GPIOs  
Supports a combination of CapSense® buttons, sliders,  
touchpads, touchscreens, and proximity sensors  
SmartSense_EMC offers superior noise immunity for  
applications with challenging conducted and radiated noise  
conditions  
2.4-GHz WirelessUSB NL Transceiver function  
Operates in the 2.4-GHz ISM Band (2.402 GHz - 2.479 GHz)  
1-Mbps over-the-air data rate  
Versatile analog system  
Low-dropout voltage regulator for all analog resources  
Receive sensitivity typical: –87 dBm  
Below 1 μA typical current consumption in sleep state  
Closed-loop frequency synthesis  
Common internal analog bus enabling capacitive sensing on  
all pins  
High power supply rejection ratio (PSRR) comparator  
8 to 10-bit incremental analog-to-digital converter (ADC)  
Supports frequency-hopping spread spectrum  
On-chip packet framer with 64-byte first in first out (FIFO)  
Additional system resources  
data buffer  
I2C slave:  
Built-in auto-retry-acknowledge protocol simplifies usage  
Built-in cyclic redundancy check (CRC), forward error  
correction (FEC), data whitening  
Additional outputs for interrupt request (IRQ) generation  
Digital readout of received signal strength indication (RSSI)  
• Selectable to 50 kHz, 100 kHz, or 400 kHz  
SPI master and slave: Configurable 46.9 kHz to 12 MHz  
Three 16-bit timers  
Watchdog and sleep timers  
Integrated supervisory circuit  
Emulated E2PROM using flash memory  
Powerful Harvard-architecture processor  
M8C CPU Up to 4 MIPS with 24 MHz Internal clock, external  
crystal resonator or clock signal  
Complete development tools  
Free development tool (PSoC Designer™)  
Full-featured, in-circuit emulator (ICE) and programmer  
Full-speed emulation  
Complex breakpoint structure  
128 KB trace memory  
Low power at high speed  
Temperature range: 0 °C to +70 °C  
Flexible on-chip memory  
• 32 KB Flash/2 KB SRAM  
50,000 flash erase/write cycles  
Partial flash updates  
Flexible protection modes  
In-system serial programming (ISSP)  
Package option  
40-pin 6 mm × 6 mm QFN  
Cypress Semiconductor Corporation  
Document Number: 001-76581 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 18, 2012  

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