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CYK128K16SCCBU-55BVI PDF预览

CYK128K16SCCBU-55BVI

更新时间: 2024-02-06 04:56:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 182K
描述
2-Mbit (128K x 16) Pseudo Static RAM

CYK128K16SCCBU-55BVI 数据手册

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CYK128K16SCCB  
2-Mbit (128K x 16) Pseudo Static RAM  
Features  
Functional Description[1]  
• Advanced low-power MoBL® architecture  
• High speed: 55 ns, 70 ns  
The CYK128K16SCCB is a high-performance CMOS pseudo  
static RAM (PSRAM) organized as 128K words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life(MoBL)  
in portable applications such as cellular telephones. The  
device can be put into standby mode, reducing power  
consumption dramatically when deselected (CE1 LOW, CE2  
HIGH or both BHE and BLE are HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when the chip is deselected (CE1 HIGH, CE2 LOW) or OE is  
deasserted HIGH), or during a write operation (Chip Enabled  
and Write Enable WE LOW). Reading from the device is  
accomplished by asserting the Chip Enables (CE1 LOW and  
CE2 HIGH) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the Truth Table for a complete description of read and write  
modes.  
• Wide voltage range: 2.7V to 3.3V  
• Typical active current: 1 mA @ f = 1 MHz  
• Low standby power  
• Automatic power-down when deselected  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
CE2  
CE1  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05525 Rev. *F  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised January 26, 2005  

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