5秒后页面跳转
CYK512K16SCAU-55BAXI PDF预览

CYK512K16SCAU-55BAXI

更新时间: 2024-01-26 12:57:28
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
10页 177K
描述
8-Mbit (512K x 16) Pseudo Static RAM

CYK512K16SCAU-55BAXI 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DSBGA包装说明:TFBGA, BGA48,6X8,30
针数:48Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83Is Samacsys:N
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e1
长度:8 mm内存密度:8388608 bit
内存集成电路类型:PSEUDO STATIC RAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:48字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:512KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.0001 A子类别:Other Memory ICs
最大压摆率:0.022 mA最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:6 mmBase Number Matches:1

CYK512K16SCAU-55BAXI 数据手册

 浏览型号CYK512K16SCAU-55BAXI的Datasheet PDF文件第2页浏览型号CYK512K16SCAU-55BAXI的Datasheet PDF文件第3页浏览型号CYK512K16SCAU-55BAXI的Datasheet PDF文件第4页浏览型号CYK512K16SCAU-55BAXI的Datasheet PDF文件第5页浏览型号CYK512K16SCAU-55BAXI的Datasheet PDF文件第6页浏览型号CYK512K16SCAU-55BAXI的Datasheet PDF文件第7页 
CYK512K16SCCA  
MoBL®  
8-Mbit (512K x 16) Pseudo Static RAM  
Features  
Functional Description[1]  
• Advanced low-power MoBL® architecture  
• High speed: 55 ns, 70 ns  
The CYK512K16SCCA is a high-performance CMOS pseudo  
static RAM (PSRAM) organized as 512K words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life(MoBL)  
in portable applications such as cellular telephones. The  
device can be put into standby mode reducing power  
consumption dramatically when deselected (CE1 LOW, CE2  
HIGH or both BHE and BLE are HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE1 HIGH, CE2 LOW), OE is deasserted  
HIGH, or during a write operation (Chip Enabled and Write  
Enable WE LOW). Reading from the device is accomplished  
by asserting the Chip Enables (CE1 LOW and CE2 HIGH) and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. If Byte Low Enable (BLE) is LOW, then data from the  
memory location specified by the address pins will appear on  
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory will appear on I/O8 to I/O15. See the Truth Table for a  
complete description of read and write modes.  
• Wide voltage range: 2.7V to 3.3V  
• Typical active current: 2 mA @ f = 1 MHz  
• Typical active current: 11 mA @ f = fMAX  
• Low standby power  
• Automatic power-down when deselected  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
512K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
CE2  
CE1  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05425 Rev. *E  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised January 25, 2005  

与CYK512K16SCAU-55BAXI相关器件

型号 品牌 描述 获取价格 数据表
CYK512K16SCAU-70BAXI CYPRESS 8-Mbit (512K x 16) Pseudo Static RAM

获取价格

CYK512K16SCAU-70BAXIT CYPRESS 暂无描述

获取价格

CYK512K16SCCA CYPRESS 8-Mbit (512K x 16) Pseudo Static RAM

获取价格

CYK512K16SCCA-55BAI CYPRESS Pseudo Static RAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, FBGA-48

获取价格

CYK512K16SCCA-70BAI CYPRESS Pseudo Static RAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, FBGA-48

获取价格

CYK512K16SCCAU ETC Memory

获取价格