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CYK256K16MCCBU-70BVXI PDF预览

CYK256K16MCCBU-70BVXI

更新时间： 2024-02-28 19:57:22
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路
页数 文件大小 规格书
10页 374K
描述
Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48

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CYK256K16MCCBU-70BVXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA,
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84最长访问时间：70 ns
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8 mm内存密度：4194304 bit
内存集成电路类型：PSEUDO STATIC RAM内存宽度：16
功能数量：1端子数量：48
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-25 °C组织：256KX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：6 mm

CYK256K16MCCBU-70BVXI 数据手册

 浏览型号CYK256K16MCCBU-70BVXI的Datasheet PDF文件第2页浏览型号CYK256K16MCCBU-70BVXI的Datasheet PDF文件第3页浏览型号CYK256K16MCCBU-70BVXI的Datasheet PDF文件第4页浏览型号CYK256K16MCCBU-70BVXI的Datasheet PDF文件第5页浏览型号CYK256K16MCCBU-70BVXI的Datasheet PDF文件第6页浏览型号CYK256K16MCCBU-70BVXI的Datasheet PDF文件第7页 
CYK256K16MCCB  
MoBL3™  
4-Mbit (256K x 16) Pseudo Static RAM  
can be put into standby mode when deselected (CE HIGH or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE HIGH), outputs are disabled (OE HIGH), both  
Byte High Enable and Byte Low Enable are disabled (BHE,  
BLE HIGH), or during a write operation (CE LOW and WE  
LOW).  
Features  
• Wide voltage range: 2.70V–3.30V  
• Access time: 55 ns, 60 ns and 70 ns  
• Ultra-low active power  
— Typical active current: 1 mA @ f = 1 MHz  
— Typical active current: 8 mA @ f = fmax (70-ns speed)  
• Ultra low standby power  
Writing to the device is accomplished by taking Chip Enable  
(CE LOW) and Write Enable (WE) input LOW. If Byte Low  
Enable (BLE) is LOW, then data from I/O pins (I/O0 through  
I/O7) is written into the location specified on the address pins  
(A0 through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in a 48-ball BGA package  
Reading from the device is accomplished by taking Chip  
Enable (CE LOW) and Output Enable (OE) LOW while forcing  
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. Refer to the truth table for a complete description of read  
and write modes.  
Functional Description[1]  
The CYK256K16MCCB is a high-performance CMOS Pseudo  
static RAM organized as 256K words by 16 bits that supports  
an asynchronous memory interface. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
256K × 16  
RAM Array  
I/O0 – I/O7  
I/O8 – I/O15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Power-Down  
Circuit  
BHE  
BLE  
CE  
Note:  
1. For best practice recommendations, please refer to the CY application note System Design Guidelines on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05585 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 18, 2006  
1234567...10

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