Datasheet > CYK128K16SCBU-70BVXI

CYK128K16SCBU-70BVXI

更新时间： 2024-11-27 03:11:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	182K
描述
2-Mbit (128K x 16) Pseudo Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CYK128K16SCBU-70BVXI 数据手册

浏览型号CYK128K16SCBU-70BVXI的Datasheet PDF文件第2页

浏览型号CYK128K16SCBU-70BVXI的Datasheet PDF文件第3页

浏览型号CYK128K16SCBU-70BVXI的Datasheet PDF文件第4页

浏览型号CYK128K16SCBU-70BVXI的Datasheet PDF文件第5页

浏览型号CYK128K16SCBU-70BVXI的Datasheet PDF文件第6页

浏览型号CYK128K16SCBU-70BVXI的Datasheet PDF文件第7页

CYK128K16SCCB

2-Mbit (128K x 16) Pseudo Static RAM

Features

Functional Description^[1]

• Advanced low-power MoBL^®architecture

• High speed: 55 ns, 70 ns

The CYK128K16SCCB is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 128K words by 16 bits that

supports an asynchronous memory interface. This device

features advanced circuit design to provide ultra-low active

current. This is ideal for providing More Battery Life™ (MoBL)

in portable applications such as cellular telephones. The

device can be put into standby mode, reducing power

consumption dramatically when deselected (CE₁LOW, CE₂

HIGH or both BHE and BLE are HIGH). The input/output pins

(I/O₀through I/O₁₅) are placed in a high-impedance state

when the chip is deselected (CE₁HIGH, CE₂LOW) or OE is

deasserted HIGH), or during a write operation (Chip Enabled

and Write Enable WE LOW). Reading from the device is

accomplished by asserting the Chip Enables (CE₁LOW and

CE₂HIGH) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the Truth Table for a complete description of read and write

modes.

• Wide voltage range: 2.7V to 3.3V

• Typical active current: 1 mA @ f = 1 MHz

• Low standby power

• Automatic power-down when deselected

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

128K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

CE₂

CE₁

BLE

CE₂

CE₁

Power -Down

Circuit

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05525 Rev. *F

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 26, 2005

12 3 4 5 6 7...10

中文翻译

下载PDF

与CYK128K16SCBU-70BVXI相关器件

型号	品牌	获取价格	描述	数据表
CYK128K16SCCB	CYPRESS	获取价格	2-Mbit (128K x 16) Pseudo Static RAM
CYK128K16SCCBU-55BVI	CYPRESS	获取价格	2-Mbit (128K x 16) Pseudo Static RAM
CYK128K16SCCBU-55BVXI	CYPRESS	获取价格	Pseudo Static RAM, 128KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CYK128K16SCCBU-70BVI	CYPRESS	获取价格	2-Mbit (128K x 16) Pseudo Static RAM
CYK128K16SCCBU-70BVXI	CYPRESS	获取价格	Pseudo Static RAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CYK-16R-21G	MERRIMAC	获取价格	DIRECTIONAL COUPLERS
CYK256K16MCB-70BVXI	CYPRESS	获取价格	Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYK256K16MCBU-55BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Pseudo Static RAM
CYK256K16MCBU-70BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Pseudo Static RAM
CYK256K16MCCB	CYPRESS	获取价格	4-Mbit (256K x 16) Pseudo Static RAM

与CYK128K16SCBU-70BVXI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

46
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

35
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

64
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

61

产品中心

服务支持

精选活动

关于我们

帮助中心

CYK128K16SCBU-70BVXI

CYK128K16SCBU-70BVXI 数据手册

与CYK128K16SCBU-70BVXI相关器件

与CYK128K16SCBU-70BVXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CYK128K16SCBU-70BVXI

CYK128K16SCBU-70BVXI 数据手册

与CYK128K16SCBU-70BVXI相关器件

与CYK128K16SCBU-70BVXI相关文章

您还可以找

您在本页遇到什么问题？