Datasheet > CYD02S18V

CYD02S18V

更新时间： 2024-11-05 03:27:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
26页	587K
描述
FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM

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CYD02S18V 数据手册

CYD01S18V/CYD02S18V

CYD04S18V/CYD09S18V

FLEx18™ 3.3V 64K/128K/256K/512K x 18

Synchronous Dual-Port RAM

Functional Description

Features

• True dual-ported memory cells that allow simultaneous

access of the same memory location

The FLEx18™ family includes 1-Mbit, 2-Mbit, 4-Mbit and

9-Mbit pipelined, synchronous, true dual-port static RAMs that

are high-speed, low-power 3.3V CMOS. Two ports are

provided, permitting independent, simultaneous access to any

location in memory. The result of writing to the same location

by more than one port at the same time is undefined. Registers

on control, address, and data lines allow for minimal set-up

and hold time.

• Synchronous pipelined operation

• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits

devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal Write pulse width is

independent of the duration of the R/W input signal. The

internal Write pulse is self-timed to allow the shortest possible

cycle times.

• 3.3V low power

— Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

• Mailbox function for message passing

• Global master reset

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 256-ball FBGA (1 mm pitch)

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

• Counter wrap-around control

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

The CYD09S18V device in this family has limited features.

Please see Address Counter and Mask Register Operations

on page 5 for details.

• Dual Chip Enables on both ports for easy depth

expansion

Seamless Migration to Next Generation Dual Port Family

• Seamless migration to next-generation dual-port family

Cypress offers a migration path for all devices in this family to

the next-generation devices in the Dual-Port family with a

compatible footprint. Please contact Cypress Sales for more

details.

Table 1. Product Selection Guide

1 Mbit

2 Mbit

4 Mbit

9 Mbit

Density

(64K x 18)

CYD01S18V

167

(128K x 18)

(256K x 18)

(512K x 18)

Part Number

CYD02S18V

167

CYD04S18V

167

CYD09S18V

133

Max. Speed (MHz)

Max. Access Time – Clock to Data (ns)

Typical operating current (mA)

Package

4.0

4.7

225

270

256FBGA

(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm)

Cypress Semiconductor Corporation

Document #: 38-06077 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised May 5, 2005

12 3 4 5 6 7...26

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与CYD02S18V相关器件

型号	品牌	获取价格	描述	数据表
CYD02S18V-133BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchron
CYD02S18V-133BBC	ROCHESTER	获取价格	128KX18 DUAL-PORT SRAM, 4ns, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CYD02S18V-133BBI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchron
CYD02S18V-167BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchron
CYD02S18V-167BBC	ROCHESTER	获取价格	128KX18 DUAL-PORT SRAM, 4ns, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CYD02S36V	CYPRESS	获取价格	FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
CYD02S36V_11	CYPRESS	获取价格	FLEx36? 3.3 V (64K x 36) Synchronous Dual-Port RAM
CYD02S36V_13	CYPRESS	获取价格	FLEx36â¢ 3.3 V (64K x 36) Synchronous Dual-P
CYD02S36V-133BBC	CYPRESS	获取价格	FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
CYD02S36V-133BBI	CYPRESS	获取价格	FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM

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