Datasheet > CYD02S36V

CYD02S36V

更新时间： 2024-11-05 03:27:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
28页	472K
描述
FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM

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CYD02S36V 数据手册

CYD01S36V

CYD02S36V/CYD04S36V

CYD09S36V/CYD18S36V

PRELIMINARY

FLEx36 3.3V 32K/64K/128K/256K/512 x 36

Synchronous Dual-Port RAM

Functional Description

Features

• True dual-ported memory cells that allow simultaneous

access of the same memory location

The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and

18-Mbit pipelined, synchronous, true dual-port static RAMs

that are high-speed, low-power 3.3V CMOS. Two ports are

provided, permitting independent, simultaneous access to any

location in memory. A particular port can write to a certain

location while another port is reading that location. The result

of writing to the same location by more than one port at the

same time is undefined. Registers on control, address, and

data lines allow for minimal set-up and hold time.

• Synchronous pipelined operation

• Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit

devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal Write pulse width is

independent of the duration of the R/W input signal. The

internal Write pulse is self-timed to allow the shortest possible

cycle times.

• 3.3V low power

— Active as low as 225 mA (typ.)

— Standby as low as 55 mA (typ.)

• Mailbox function for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 256-ball FBGA (1-mm pitch)

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

• Counter wrap around control

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

The CYD18S36V devices in this family has limited features.

Please see Address Counter and Mask Register Opera-

tions^[18]on page 5 for details.

• Dual Chip Enables on both ports for easy depth

expansion

Seamless Migration to Next-Generation Dual-Port Family

• Seamless migration to next-generation dual-port family

Cypress offers a migration path for all devices in this family to

the next-generation devices in the Dual-Port family with a

compatible footprint. Please contact Cypress Sales for more

details.

Table 1. Product Selection Guide

Density

1 Mbit

(32K x 36)

2 Mbit

(64K x 36)

4 Mbit

(128K x 36)

9 Mbit

(256K x 36)

18 Mbit

(512K x 36)

Part Number

CYD01S36V

CYD02S36V

CYD04S36V

CYD09S36V

CYD18S36V

Max. Speed (MHz)

167

4.0

167

4.0

167

4.0

167

4.0

133

5.0

Max. Access Time – Clock to Data

(ns)

Typical Operating Current (mA)

Package

225

270

315

256 FBGA

(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (23 mm x 23 mm)

Cypress Semiconductor Corporation

Document #: 38-06076 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 27, 2005

12 3 4 5 6 7...28

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与CYD02S36V相关器件

型号	品牌	获取价格	描述	数据表
CYD02S36V_11	CYPRESS	获取价格	FLEx36? 3.3 V (64K x 36) Synchronous Dual-Port RAM
CYD02S36V_13	CYPRESS	获取价格	FLEx36â¢ 3.3 V (64K x 36) Synchronous Dual-P
CYD02S36V-133BBC	CYPRESS	获取价格	FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
CYD02S36V-133BBI	CYPRESS	获取价格	FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
CYD02S36V-167BBC	CYPRESS	获取价格	FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
CYD02S36V18	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM
CYD02S36V18-167BBXI	CYPRESS	获取价格	Dual-Port SRAM, 64KX36, 4ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FBG
CYD02S36V18-200BBC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM
CYD02S36V18-200BBXC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM
CYD02S36VA-167BBC	CYPRESS	获取价格	FLEx36? 3.3 V (64K x 36) Synchronous Dual-Port RAM

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