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CYD02S36V18-167BBXI PDF预览

CYD02S36V18-167BBXI

更新时间： 2024-11-06 10:53:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
52页 1093K
描述
Dual-Port SRAM, 64KX36, 4ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FBGA-256

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CYD02S36V18-167BBXI 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LBGA, BGA256,16X16,40
针数：256Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.52最长访问时间：4 ns
其他特性：PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：S-PBGA-B256
JESD-609代码：e1长度：17 mm
内存密度：2359296 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端口数量：2
端子数量：256字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA256,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
电源：1.5/1.8 V认证状态：Not Qualified
座面最大高度：1.7 mm最大待机电流：0.35 A
最小待机电流：1.4 V子类别：SRAMs
最大压摆率：0.78 mA最大供电电压 (Vsup)：1.58 V
最小供电电压 (Vsup)：1.42 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：17 mm
Base Number Matches：1

CYD02S36V18-167BBXI 数据手册

 浏览型号CYD02S36V18-167BBXI的Datasheet PDF文件第2页浏览型号CYD02S36V18-167BBXI的Datasheet PDF文件第3页浏览型号CYD02S36V18-167BBXI的Datasheet PDF文件第4页浏览型号CYD02S36V18-167BBXI的Datasheet PDF文件第5页浏览型号CYD02S36V18-167BBXI的Datasheet PDF文件第6页浏览型号CYD02S36V18-167BBXI的Datasheet PDF文件第7页 
FullFlex  
FullFlex™ Synchronous SDR Dual Port SRAM  
Features  
Functional Description  
■ True dual port memory enables simultaneous access to the  
shared array from each port  
The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,  
9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static  
RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two  
ports are provided, enabling simultaneous access to the array.  
Simultaneous access to a location triggers deterministic access  
control. For FullFlex72 these ports operate independently with  
72-bit bus widths and each port is independently configured for  
two pipelined stages. Each port is also configured to operate in  
pipelined or flow through mode.  
■ Synchronous pipelined operation with Single Data Rate (SDR)  
operation on each port  
❐ SDR interface at 200 MHz  
❐ Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)  
■ Selectable pipelined or flow-through mode  
■ 1.5V or 1.8V core power supply  
The advanced features include the following:  
■ Commercial and Industrial temperature  
■ IEEE 1149.1 JTAG boundary scan  
■ Built in deterministic access control to manage address colli-  
sions during simultaneous access tothesamememorylocation  
■ Variable Impedance Matching (VIM) to improve data trans-  
mission by matching the output driver impedance to the line  
impedance  
■ Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and  
x18) packages  
■ FullFlex72 family  
■ Echo clocks to improve data transfer  
❐ 36 Mbit: 512K x 72 (CYD36S72V18)  
❐ 18 Mbit: 256K x 72 (CYD18S72V18)  
❐ 9 Mbit: 128K x 72 (CYD09S72V18)  
❐ 4 Mbit: 64K x 72 (CYD04S72V18)  
To reduce the static power consumption, chip enables power  
down the internal circuitry. The number of latency cycles before  
a change in CE0 or CE1 enables or disables the databus  
matches the number of cycles of read latency selected for the  
device. For a valid write or read to occur, activate both chip  
enable inputs on a port.  
■ FullFlex36 family  
❐ 36 Mbit: 1M x 36 (CYD36S36V18)  
❐ 18 Mbit: 512K x 36 (CYD18S36V18)  
❐ 9 Mbit: 256K x 36 (CYD09S36V18)  
❐ 4 Mbit: 128K x 36 (CYD04S36V18)  
❐ 2 Mbit: 64K x 36 (CYD02S36V18)  
Each port contains an optional burst counter on the input address  
register. After externally loading the counter with the initial  
address, the counter increments the address internally.  
Additional device features include a mask register and a mirror  
register to control counter increments and wrap around. The  
counter interrupt (CNTINT) flags notify the host that the counter  
reaches maximum count value on the next clock cycle. The host  
reads the burst counter internal address, mask register address,  
and busy address on the address lines. The host also loads the  
counter with the address stored in the mirror register by using the  
retransmit functionality. Mailbox interrupt flags are used for  
message passing, and JTAG boundary scan and asynchronous  
Master Reset (MRST) are also available. The Logic Block  
Diagram on page 2 shows these features.  
■ FullFlex18 family  
❐ 36 Mbit: 2M x 18 (CYD36S18V18)  
❐ 18 Mbit: 1M x 18 (CYD18S18V18)  
❐ 9 Mbit: 512K x 18 (CYD09S18V18)  
❐ 4 Mbit: 256K x 18 (CYD04S18V18)  
■ Built in deterministic access control to manage address colli-  
sions  
❐ Deterministic flag output upon collision detection  
❐ Collision detection on back-to-back clock cycles  
❐ First Busy Address readback  
The FullFlex72 is offered in a 484-Ball plastic BGA package. The  
FullFlex36 and FullFlex18 are available in 256-Ball fine pitch  
BGA package.  
■ Advanced features for improved high speed data transfer and  
flexibility  
❐ Variable Impedance Matching (VIM)  
❐ Echo clocks  
❐ Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V  
LVCMOS, or 2.5V LVCMOS IO on each port  
❐ Burst counters for sequential memory access  
❐ Mailbox with interrupt flags for message passing  
❐ Dual Chip Enables for easy depth expansion  
Cypress Semiconductor Corporation  
Document Number: 38-06082 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 15, 2008  
[+] Feedback  
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CYD04S18V-167BBC CYPRESS

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 		FLEx18⑩ 3.3V 64K/128K/256K/512K x 18 Synchron
CYD04S18V18 CYPRESS

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CYD04S18V18-167BBI CYPRESS

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 		Dual-Port SRAM, 256KX18, 11ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256

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