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CYBUS3384LMB PDF预览

CYBUS3384LMB

更新时间： 2024-11-04 23:45:51
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Bus Switch

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CYBUS3384LMB 数据手册

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1CYBUS3L384  
CYBUS3384  
CYBUS3L384  
Dual 5-Bit Bus Switch  
Features  
Functional Description  
• Zero propagation delay  
The CYBUS3384 and CYBUS3L384 are ten-bit, two-port bidi-  
rectional bus switches that allow one bus to be connected di-  
rectly to, or isolated from, another without introducing addition-  
al propagation delay or ground noise. The input and output  
voltage levels allow direct interface with TTL and CMOS de-  
• 2Ω switches connect inputs to outputs  
• Direct bus connection when switches are ON  
• High (>500 Meg Ω) resistance when switch is OFF  
• Performs bidirectional translator function between  
3.3V and 5.0V power supplies  
• CMOS for low power dissipation  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
vices. Two bus enable signals, BE and BE , turn on the upper  
1
2
and lower five bits, respectively.  
Designed with a low resistance of 2Ω, the CYBUS3384 and  
CYBUS3L384 are ideal for use in VME or other high DC drive  
applications.  
• Inputs and outputs interface with 5.0V CMOS, TTL, or  
3.3V CMOS  
• ESD > 2000V  
The power-off disable feature enables modules and cards to  
be either inserted or withdrawn from operating equipment  
without shutting down power. Additionally, they facilitate bidi-  
rectional interfacing between 3.3V and 5V systems by placing  
• Power-off disable  
a single diode in series with the 5V V line and a resistor from  
pin 24 to ground.  
CC  
CYBUS3L384  
• Low power version  
The CYBUS3384 and CYBUS3L384 are also suitable for  
small signal analog application where crosstalk and off isola-  
tion performance of –66 dB at 50 MHz is required.  
The CYBUS3L384 is a low-power version of the CYBUS3384  
with a typical I of 0.2 µA.  
CC  
Logic Block Diagram  
Pin Configurations  
BE  
1
DIP/SOIC/QSOP  
Top View  
BE  
2
1
BE  
1
24  
V
CC  
A
B
B
B
0
0
1
2
2
3
4
5
6
B
B
9
23  
22  
21  
0
A
0
A
9
A
1
A
8
A
1
B
B
1
20  
19  
18  
17  
16  
A
2
8
B
A
B
2
7
A
3
A
7
B
B
2
7
8
9
3
4
A
3
A
6
A
4
B
3
4
B
6
B
10  
11  
12  
B
A
5
15  
14  
A
5
B
B
B
5
6
A
4
5
GND  
BE  
2
13  
A
6
BUS3384-2  
A
7
7
8
9
A
8
B
B
BUS3384-1  
A
9
Function Table[1]  
Pin Description  
Inputs  
Name  
Description  
BE  
H
L
BE  
H
H
L
B
B
Function  
Non-connect  
Connect  
A
B
Bus A, Inputs or Outputs  
Bus B, Inputs or Outputs  
Bus Switch Enable  
1
2
0–4  
5–9  
High-Z  
High-Z  
A
High-Z  
BE , BE  
0–4  
1
2
H
L
High-Z  
A
A
Connect  
5–9  
L
A
Connect  
0–4  
5–9  
Note:  
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
May 1994 – Revised March 1996  
•
408-943-2600  
12345678

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