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CY8C21434-12X14I PDF预览

CY8C21434-12X14I

更新时间: 2024-09-16 14:48:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
55页 1531K
描述
Multifunction Peripheral, CMOS,

CY8C21434-12X14I 技术参数

生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.68其他特性:ALSO AVAILABE WITH 3.3V AND 5V SUPPLY
地址总线宽度:边界扫描:NO
总线兼容性:I2C; SPI; UART最大时钟频率:24.6 MHz
外部数据总线宽度:JESD-30 代码:R-XUUC-N
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
RAM(字数):512最大供电电压:5.25 V
最小供电电压:2.4 V标称供电电压:2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

CY8C21434-12X14I 数据手册

 浏览型号CY8C21434-12X14I的Datasheet PDF文件第2页浏览型号CY8C21434-12X14I的Datasheet PDF文件第3页浏览型号CY8C21434-12X14I的Datasheet PDF文件第4页浏览型号CY8C21434-12X14I的Datasheet PDF文件第5页浏览型号CY8C21434-12X14I的Datasheet PDF文件第6页浏览型号CY8C21434-12X14I的Datasheet PDF文件第7页 
CY8C21634, CY8C21534, CY8C21434  
CY8C21334, CY8C21234  
PSoC® Programmable System-on-Chip™  
PSoC® Programmable System-on-Chip™  
Up to eight analog inputs on GPIOs  
Configurable interrupt on all GPIOs  
Features  
Powerful Harvard-architecture processor  
M8C processor speeds up to 24 MHz  
Low power at high speed  
Operating voltage: 2.4 V to 5.25 V  
Operating voltages down to 1.0 V using on-chip switch mode  
pump (SMP)  
Industrial temperature range: –40 °C to +85 °C  
Advanced peripherals (PSoC® blocks)  
Four analog Type E PSoC blocks provide:  
• Two comparators with digital-to-analog converter (DAC)  
references  
Versatile analog mux  
Common internal analog bus  
Simultaneous connection of I/O combinations  
Capacitive sensing application capability  
Additional system resources  
I2C [2] master, slave, and multi-master to 400 kHz  
Watchdog and sleep timers  
User-configurable low-voltage detection (LVD)  
Integrated supervisory circuit  
On-chip precision voltage reference  
• Single or dual 10-bit 28 channel analog-to-digital  
converters (ADC)  
Four digital PSoC blocks provide:  
• 8- to 32-bit timers, counters, and pulse width modulators  
(PWMs)  
Logic Block Diagram  
• Cyclical redundancy check (CRC) and pseudo random  
sequence (PRS) modules  
• Full-duplex universal asynchronous receiver transmitter  
(UART), serial peripheral interface (SPI) master or slave  
• Connectable to all general purpose I/O (GPIO) pins  
Complex peripherals by combining blocks  
Flexible on-chip memory  
8 KB flash program storage 50,000 erase/write cycles  
512 bytes static random access memory (SRAM) data  
storage  
In-system serial programming (ISSP)  
Partial flash updates  
Flexible protection modes  
EEPROM emulation in flash  
Complete development tools  
Free development software (PSoC Designer™)  
Full-featured, in-circuit emulator (ICE) and programmer  
Full-speed emulation  
Complex breakpoint structure  
128-KB trace memory  
Precision, programmable clocking  
Internal ±2.5% 24- / 48-MHz main oscillator [1]  
Internal oscillator for watchdog and sleep  
Programmable pin configurations  
25-mA sink, 10-mA source on all GPIOs  
Pull-up, pull-down, high Z, strong, or open-drain drive modes  
on all GPIOs  
Errata: For information on silicon errata, see “Errata” on page 49. Details include trigger conditions, devices affected, and proposed workaround.  
Notes  
1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.  
2
2
2. Errata:The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is transitioning in to or out of sleep  
mode.  
Cypress Semiconductor Corporation  
Document Number: 38-12025 Rev. AD  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 15, 2014  

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