PSoC™ Mixed-Signal Array
Final Data Sheet
CY8C21234, CY8C21334,
CY8C21434, CY8C21534, and CY8C21634
Features
■ Powerful Harvard Architecture Processor
■ M8C Processor Speeds to 24 MHz
■ Low Power at High Speed
■ Flexible On-Chip Memory
■ Programmable Pin Configurations
■ 25 mA Drive on All GPIO
■ 8K Flash Program Storage 50,000 Erase/Write
Cycles
■ Pull Up, Pull Down, High Z, Strong, or Open
■ 512 Bytes SRAM Data Storage
■ In-System Serial Programming (ISSP™)
■ Partial Flash Updates
Drain Drive Modes on All GPIO
■ 2.4V to 5.25V Operating Voltage
■ Up to 8 Analog Inputs on GPIO
■ Configurable Interrupt on All GPIO
■ Versatile Analog Mux
■ Operating Voltages Down to 1.0V Using
On-Chip Switch Mode Pump (SMP)
■ Industrial Temperature Range: -40°C to +85°C
■ Flexible Protection Modes
■ EEPROM Emulation in Flash
■ Common Internal Analog Bus
■ Advanced Peripherals (PSoC Blocks)
■ 4 Analog Type “E” PSoC Blocks Provide:
■ Simultaneous Connection of IO Combinations
■ Capacitive Sensing Application Capability
■ Additional System Resources
■ Complete Development Tools
■ Free Development Software
- 2 Comparators with DAC Refs
- Single or Dual 8-Bit 28 Channel ADC
■ 4 Digital PSoC Blocks Provide:
(PSoC™ Designer)
■ Full-Featured, In-Circuit Emulator and
■ I2C™ Master, Slave and Multi-Master to
Programmer
400 kHz
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
■ Full Speed Emulation
■ Watchdog and Sleep Timers
■ Complex Breakpoint Structure
■ 128K Trace Memory
■ User-Configurable Low Voltage Detection
■ Integrated Supervisory Circuit
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
■ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
■ Internal ±2.5% 24/48 MHz Oscillator
■ Internal Oscillator for Watchdog and Sleep
■ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Port 3 Port 2 Port 1 Port 0
PSoC
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
CORE
SystemBus
Global Digital
Interconnect
Global Analog Interconnect
Flash 8K
CPUCore
SRAM
512 Bytes
SROM
Sleep and
Watchdog
Interrupt
Controller
(M8C)
Clock Sources
(Includes IMO and ILO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each CY8C21x34 PSoC device
includes four digital blocks and four analog blocks. Depending
on the PSoC package, up to 28 general purpose IO (GPIO) are
also included. The GPIO provide access to the global digital
and analog interconnects.
ANALOG SYSTEM
DIGITAL SYSTEM
Analog
Ref.
Analog
Digital
PSoC
Block
Array
PSoC
Block
Array
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
POR and LVD
System Resets
Sw itch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks
Analog
Mux
I2C
SYSTEM RESOURCES
April 20, 2005
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12025 Rev. *G
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