CY8C21345
CY8C22345, CY8C22545
®
PSoC Programmable System-on-Chip
■ Programmable pin configurations:
❐ 25 mA sink, 10 mA source on all GPIOs
Features
■ Powerful Harvard-architecture processor:
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Pull-up, pull-down, high Z, Strong, or open-drain drive modes
on all GPIOs
❐ Up to 38 analog inputs on GPIOs
❐ Configurable interrupt on all GPIOs
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: -40°C to +85°C
■ Advanced peripherals (PSoC® Blocks)
❐ Six analog type “E” PSoC blocks provide:
• Single or dual 8-Bit ADC
• Comparators (up to four)
❐ Up to eight digital PSoC blocks provide:
• 8 to 32-Bit Timers, counters, and PWMs
■ Additional system resources:
❐ I2C™ slave, master, and multimaster to 400 kHz
❐ Supports hardware addressing feature
❐ Watchdog and sleep timers
❐ User configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-Chip precision voltage reference
❐ Supports RTC block into digital peripheral logic
• One shot, multi shot mode support in timers and PWMs
• PWM with deadband support in one digital block
• Shift register, CRC, and PRS modules
• Full duplex UART
Top Level Block Diagram
Analog
Drivers
Port 4
Port 3
Port 2 Port 1 Port 0
• Multiple SPI masters or slaves, variable data length
Support: 8- to 16-Bit
PSoC Core
• Can be connected to all GPIO pins
❐ Complex peripherals by combining blocks
❐ Shift function support for FSK detection
❐ Powerful synchronize feature support. Analog module
operations can be synchronized by digital blocks or external
signals.
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
SRAM
1K
SROM
Sleep and
Watchdog
CPU Core (M8C)
■ High speed 10-bit SAR ADC with sample and hold optimized for
embedded control
Interrupt
Controller
■ Precision, programmable clocking:
❐ Internal ± 5% 24/48 MHz oscillator across the industrial
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
temperature range
ANALOG SYSTEM
❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal/external oscillator for watchdog and sleep
DIGITAL SYSTEM
Digital Block Array
Analog Input
Muxing(L,R)
Analog
Ref
=
DBC DBC DCC DCC
ROW 1
■ Flexible on-chip memory:
❐ Up to 16 KB flash program storage 50,000 erase/write cycles
❐ Up to 1-KB SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Analog Block Array
CTE CTE CTE CTE
SCE SCE
DBC DBC DCC DCC
ROW 2
CapSense
Digital Resource
10-bit SAR
ADC
■ Optimized CapSense® resource:
❐ Two IDAC support up to 640 µA source current to replace
external resistor
❐ Two dedicated clock resources for CapSense:
• CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK
• CNT_CLK: 1/2/4/8 Derive from CSD_CLK
POR and LVD
System Resets
Internal
Voltage
Ref.
I2C
Digital
Clocks
MACs
❐ Dedicated 16-bit timers/counters for capsense scanning
❐ Support dual CSD channels simultaneous scanning
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-43084 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2011
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