CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Automotive PSoC®
Programmable System-on-Chip™
Automotive PSoC® Programmable System-on-Chip™
❐ Two current DACs provide programmable sensor tuning in
Features
firmware
■ Automotive Electronics Council (AEC) Q100 qualified
❐ Two dedicated clock resources for CapSense
■ Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Two dedicated 16-bit timers/counters for CapSense
scanning
■ Versatile analog mux
❐ Common internal analog bus
❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to
❐ Simultaneous connection of I/O combinations
■ Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Analog input on all GPIOs
❐ Configurable interrupt on all GPIOs
■ Additional system resources:
❐ I2C master, slave, or multi-master
• Operation up to 400 kHz
• Hardware address detection feature
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
❐ Hardware real time clock (RTC) block
+85 °C temperature range
❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to
+125 °C temperature range
■ Advanced peripherals (PSoC® blocks)
❐ Six analog Type ‘E’ PSoC blocks provide:
• Up to four comparators with digital-to-analog converters
(DAC) references
• Up to 10-bit single or dual analog-to-digital converters
(ADCs)
❐ Up to eight digital PSoC blocks provide:
• 8 to 32-bit timers, counters, and pulse width modulators
(PWMs)
• One-shot, multi-shot mode in timers and PWMs
• PWM with deadband in one digital block
• Shift register, cyclical redundancy check (CRC), and
pseudo random sequence (PRS) modules
• Full- or half-duplex UARTs
• SPI masters or slaves, 8- to 16-bit variable data length
• Connectable to all general-purpose I/O (GPIO) pins
Block Diagram
Port 4 Port 3 Port 2 Port 1 Port 0
PSoC CORE
❐ Complex peripherals by combining blocks
❐ Powerful synchronization support, analog module operations
can be synchronized by digital blocks or external signals.
System Bus
Global Digital
■ High-speed 10-bit successive approximation register (SAR)
ADC with sample and hold optimized for embedded control
Global Analog Interconnect
Interconnect
■ CY8C22345H devices Integrate Immersion® TouchSense®
SROM Flash 16K/8K
1KB/512B
SRAM
Haptics Technology for ERM drive control
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
■ Precision, programmable clocking
❐ Internal oscillator up to 24 MHz
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
❐ High accuracy 24 MHz with optional 32-kHz crystal and
phase locked loop (PLL)
DIGITAL SYSTEM
ANALOG SYSTEM
❐ Optional external oscillator, up to 24 MHz
Analog
Ref
❐ Internal low speed, low-power oscillator for watchdog and
10-bit SAR
ADC
sleep functionality
Digital Block
Array
■ Flexible on-chip memory
Analog
Input
❐ Up to 16 KB flash program storage, 1000 erase/write cycles
❐ Up to 1 KB SRAM data storage
❐ In-System Serial Programming (ISSP)
❐ Partial flash updates
Muxing
Analog
Block
Array
CapSense Digital
Resources
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Optimized CapSense® resource
❐ Supports two CapSense channels with simultaneous
scanning
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum.
I2C
RTC
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-55397 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 4, 2012
5秒后页面跳转
SK海力士量产12层HBM3E，容量高达36GB
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
贸泽上架Tallysman TW5386智能GNSS天线
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
