CY8C21345
CY8C22345
CY8C22545
PSoC® Programmable System-on-Chip
• CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK
• CNT_CLK: 1/2/4/8 Derive from CSD_CLK
❐ Dedicated 16-bit timers/counters for CapSense scanning
❐ Support dual CSD channels simultaneous scanning
Features
■ Powerful Harvard-architecture processor:
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: –40 °C to +85 °C
■ Advanced peripherals (PSoC® Blocks)
❐ Six analog type “E” PSoC blocks provide:
• Single or dual 8-Bit ADC
• Comparators (up to four)
❐ Up to eight digital PSoC blocks provide:
■ Programmable pin configurations:
❐ 25 mA sink, 10 mA source on all GPIOs
❐ Pull-up, pull-down, highZ, Strong, oropen-draindrivemodes
on all GPIOs
❐ Up to 38 analog inputs on GPIOs
❐ Configurable interrupt on all GPIOs
■ Additional system resources:
❐ I2C slave, master, and multimaster to 400 kHz
❐ Supports hardware addressing feature
❐ Watchdog and sleep timers
❐ User configurable low voltage detection
❐ Integrated supervisory circuit
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• One shot, multi-shot mode support in timers and PWMs
• PWM with deadband support in one digital block
• Shift register, CRC, and PRS modules
• Full duplex UART
❐ On-Chip precision voltage reference
❐ Supports RTC block into digital peripheral logic
Top Level Block Diagram
• Multiple SPI masters or slaves, variable data length
Support: 8- to 16-Bit
Analog
Port 4 Port 3 Port 2 Port 1 Port 0
Drivers
• Can be connected to all GPIO pins
PSoC Core
❐ Complex peripherals by combining blocks
❐ Shift function support for FSK detection
❐ Powerful synchronize feature support. Analog module
operations can be synchronized by digital blocks or external
signals.
Global Digital Interconnect
Global Analog Interconnect
SRAM
1K
SROM
Flash 16K
■ High speed 10-bit SAR ADC with sample and hold optimized for
embedded control
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
■ Precision, programmable clocking:
❐ Internal ± 5% [1] 24/48 MHz oscillator across the industrial
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
temperature range
❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
ANALOG SYSTEM
DIGITAL SYSTEM
Digital Block Array
Analog Input
Muxing(L,R)
Analog
Ref
=
❐ Internal/external oscillator for watchdog and sleep
DBC DBC DCC DCC
ROW 1
■ Flexible on-chip memory:
Analog Block Array
CTE CTE CTE CTE
SCE SCE
❐ Up to 16 KB flash program storage 50,000 erase/write cycles
❐ Up to 1-KB SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
DBC DBC DCC DCC
ROW 2
CapSense
Digital Resource
10-bit SAR
ADC
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Optimized CapSense® resource:
❐ Two IDAC support up to 640 µA source current to replace
external resistor
POR and LVD
System Resets
Internal
Voltage
Ref.
I2C
Digital
Clocks
MACs
❐ Two dedicated clock resources for CapSense:
SYSTEM RESOURCES
Errata: For information on silicon errata, see “Errata” on page 35. Details include trigger conditions, devices affected, and proposed workaround.
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 35.
Cypress Semiconductor Corporation
Document Number: 001-43084 Rev. *W
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 11, 2017
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