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CY8C20160-LDX2I PDF预览

CY8C20160-LDX2I

更新时间: 2024-11-24 03:12:35
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赛普拉斯 - CYPRESS /
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描述
CapSense Express ⑩-6 Configurable IOs

CY8C20160-LDX2I 数据手册

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CY8C20160  
CapSense Express ™-6 Configurable IOs  
Features  
Overview  
6 configurable IOs supporting  
CapSense buttons  
LED drive  
Interrupt outputs  
WAKE on interrupt input  
User defined input or output  
The CapSense ExpressTM controller allows the control of 6 IOs  
configurable as capacitive sensing buttons or as GPIOs for  
driving LEDs or interrupt signals based on various button  
conditions. The GPIOs are also configurable for waking up the  
device from sleep based on an interrupt input.  
The user has the ability to configure buttons, outputs, and  
parameters, through specific commands sent to the I2C port. The  
IOs have the flexibility in mapping to capacitive buttons and as  
standard GPIO functions such as interrupt output or input, LED  
drive and digital mapping of input to output using simple logical  
operations. This enables easy PCB trace routing and reduces  
the PCB size and stack up. CapSense Express products are  
designed for easy integration into complex products.  
2.4V to 5.25V operating voltage  
Industrial temperature range: –40°C to +85°C  
I2C slave interface for configuration  
Selectable to 50 kHz,100 kHz and 400 kHz.  
Reduce BOM cost  
Internal oscillator - no external oscillators or crystal  
Free development tool - no external tuning components  
Architecture  
The logic block diagram shows the internal architecture of  
CY8C20160.  
Low operating current  
Active current: continuous sensor scan:1.5 mA  
Sleep current: no scan, continuous sleep:2.6 uA  
The user can configure registers with parameters needed to  
adjust the operation and sensitivity of the CapSense system.  
CY8C20160 supports a standard I²C serial communication  
interface that allows the host to configure the device and to read  
sensor information in real time through easy register access.  
Available in 16-pin COL and 16-pin SOIC packages  
The CapSense Express Core  
The CapSense Express Core has a powerful configuration and  
control block. It encompasses SRAM for data storage, an  
interrupt controller, sleep, and watchdog timers. System  
resources provide additional capability, such as a configurable  
I2C slave communication interface and various system resets.  
The Analog System is composed of the CapSense PSoC block  
which supports capacitive sensing of up to six inputs.  
Cypress Semiconductor Corporation  
Document Number:001-17347 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 11, 2008  
[+] Feedback  

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