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CY8C20234 PDF预览

CY8C20234

更新时间: 2024-11-07 03:12:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
32页 431K
描述
PSoC㈢ Mixed-Signal Array

CY8C20234 数据手册

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PSoC® Mixed-Signal Array  
Final Data Sheet  
CY8C20234  
CY8C20334 and CY8C20434  
Features  
Low Power CapSense Block  
Complete Development Tools  
Versatile Analog Mux  
Configurable Capacitive Sensing Elements  
Free Development Tool (PSoC Designer™)  
Common Internal Analog Bus  
Supports Combination of CapSense Buttons,  
Sliders, Touchpads and Proximity Sensors  
Full-Featured, In-Circuit Emulator and  
Programmer  
Simultaneous Connection of IO Combinations  
Comparator Noise Immunity  
Full Speed Emulation  
Powerful Harvard Architecture Processor  
Low-Dropout Voltage Regulator for the Analog  
Array  
Complex Breakpoint Structure  
128K Trace Memory  
M8C Processor Speeds Running up to 12 MHz  
Low Power at High Speed  
Additional System Resources  
Configurable Communication Speeds  
-- I2C: Selectable to 50 kHz, 100 kHz or  
400 kHz  
-- SPI : Configurable between 46.9 kHz and  
3 MHz  
Precision, Programmable Clocking  
2.4V to 5.25V Operating Voltage  
Industrial Temperature Range:  
-40°C to +85°C  
Internal ±5.0% 6/12 MHz Main Oscillator  
Internal Low Speed Oscillator at 32 kHz for  
Watchdog and Sleep  
Flexible On-Chip Memory  
2
Programmable Pin Configurations  
8K Flash Program Storage  
50,000 Erase/Write Cycles  
I C™ Slave  
Pull Up, High Z, Open Drain, CMOS Drive  
Modes on All GPIO  
SPI Master and SPI Slave  
Watchdog and Sleep Timers  
Internal Voltage Reference  
Integrated Supervisory Circuit  
512 Bytes SRAM Data Storage  
Partial Flash Updates  
Up to 28 Analog Inputs on GPIO  
Configurable Inputs on All GPIO  
Flexible Protection Modes  
Interrupt Controller  
Selectable, Regulated Digital IO on Port 1  
-- 3.0V, 20 mA Total Port 1 Source Current  
-- 5 mA Strong Drive Mode on Port 1  
In-System Serial Programming (ISSP)  
PSoC® Functional Overview  
The PSoC family consists of many Mixed-Signal Array with On-  
Chip Controller devices. These devices are designed to replace  
multiple traditional MCU-based system components with one,  
low cost single-chip programmable component. A PSoC device  
includes configurable analog and digital blocks, as well as pro-  
grammable interconnect. This architecture allows the user to  
create customized peripheral configurations, to match the  
requirements of each individual application. Additionally, a fast  
CPU, Flash program memory, SRAM data memory, and config-  
urable IO are included in a range of convenient pinouts.  
The PSoC architecture for this device family, as illustrated on  
the left, is comprised of three main areas: the Core, the System  
Resources, and the CapSense Analog System. A common, ver-  
satile bus allows connection between IO and the analog sys-  
tem. Each CY8C20x34 PSoC device includes a dedicated  
CapSense block that provides sensing and scanning control cir-  
cuitry for capacitive sensing applications. Depending on the  
PSoC package, up to 28 general purpose IO (GPIO) are also  
included. The GPIO provide access to the MCU and analog  
mux.  
September 18, 2006 © Cypress Semiconductor Corp. 2005-2006 — Document No. 001-05356 Rev. *B  
1
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