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CY8C20234-12LKXI

更新时间： 2024-02-06 16:14:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
34页	860K
描述
PSoC㈢ Mixed-Signal Array

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技术参数
数据手册

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CY8C20234-12LKXI 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	SOIC	包装说明：	SOP, SOP16,.25
针数：	16	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.31.00.01
Factory Lead Time：	1 week	风险等级：	2.3
Is Samacsys：	N	Base Number Matches：	1

CY8C20234-12LKXI 数据手册

CY8C20534, CY8C20434

CY8C20334, CY8C20234

PSoC® Mixed-Signal Array

Features

■ Low Power CapSense Block

■ Precision, Programmable Clocking

❐ Configurable Capacitive Sensing Elements

❐ Supports Combination of CapSense Buttons, Sliders, Touch-

pads, and Proximity Sensors

❐ Internal ±5.0% 6/12 MHz Main Oscillator

❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and Sleep

■ Programmable Pin Configurations

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds Running up to 12 MHz

❐ Low Power at High Speed

❐ Pull Up, High Z, Open Drain, and CMOS Drive Modes on All

GPIO

❐ Up to 28 Analog Inputs on GPIO

❐ 2.4V to 5.25V Operating Voltage

❐ Configurable Inputs on All GPIO

❐ Industrial Temperature Range: -40°C to +85°C

❐ Selectable, Regulated Digital IO on Port 1

• 3.0V, 20 mA Total Port 1 Source Current

• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux

❐ Common Internal Analog Bus

❐ Simultaneous Connection of IO Combinations

❐ Comparator Noise Immunity

■ Flexible On-Chip Memory

❐ 8K Flash Program Storage

50,000 Erase/Write Cycles

❐ 512 Bytes SRAM Data Storage

❐ Partial Flash Updates

❐ Low Dropout Voltage Regulator for the Analog Array

❐ Flexible Protection Modes

❐ Interrupt Controller

❐ In-System Serial Programming (ISSP)

■ Additional System Resources

❐ Configurable Communication Speeds

• I C: Selectable to 50 kHz, 100 kHz, or 400 kHz

■ Complete Development Tools

❐ Free Development Tool (PSoC Designer™)

❐ Full Featured, In-Circuit Emulator, and

Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

• SPI: Configurable between 46.9 kHz and 3 MHz

❐ I C™ Slave

❐ SPI Master and SPI Slave

❐ Watchdog and Sleep Timers

❐ Internal Voltage Reference

❐ Integrated Supervisory Circuit

❐ 128K Trace Memory

Logic Block Diagram

Port 3 Port 2 Port 1 Port 0 Config LDO

PSoC

CORE

System Bus

Global Analog Interconnect

SRAM

512 Bytes

SROM

Flash 8K

CPU Core

(M8C)

Sleep and

Watchdog

Interrupt

Controller

6/12 MHz Internal Main Oscillator

Analog

Ref.

ANALOG

SYSTEM

CapSense

Block

POR and LVD

System Resets

I2C Slave/SPI

Master-Slave

Analog

Mux

SYSTEM RESOURCES

Cypress Semiconductor Corporation

Document Number: 001-05356 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 12, 2007

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