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CY8C20160-SX2I PDF预览

CY8C20160-SX2I

更新时间: 2024-11-27 03:12:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 335K
描述
CapSense Express ⑩-6 Configurable IOs

CY8C20160-SX2I 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-16
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:8.42其他特性:SRAM IS ORGANISED AS 512MB
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.893 mm内存密度:2048 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:1
湿度敏感等级:3功能数量:1
端子数量:16字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2KX1封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.727 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

CY8C20160-SX2I 数据手册

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CY8C20160  
CapSense Express ™-6 Configurable IOs  
Features  
Overview  
6 configurable IOs supporting  
CapSense buttons  
LED drive  
Interrupt outputs  
WAKE on interrupt input  
User defined input or output  
The CapSense ExpressTM controller allows the control of 6 IOs  
configurable as capacitive sensing buttons or as GPIOs for  
driving LEDs or interrupt signals based on various button  
conditions. The GPIOs are also configurable for waking up the  
device from sleep based on an interrupt input.  
The user has the ability to configure buttons, outputs, and  
parameters, through specific commands sent to the I2C port. The  
IOs have the flexibility in mapping to capacitive buttons and as  
standard GPIO functions such as interrupt output or input, LED  
drive and digital mapping of input to output using simple logical  
operations. This enables easy PCB trace routing and reduces  
the PCB size and stack up. CapSense Express products are  
designed for easy integration into complex products.  
2.4V to 5.25V operating voltage  
Industrial temperature range: –40°C to +85°C  
I2C slave interface for configuration  
Selectable to 50 kHz,100 kHz and 400 kHz.  
Reduce BOM cost  
Internal oscillator - no external oscillators or crystal  
Free development tool - no external tuning components  
Architecture  
The logic block diagram shows the internal architecture of  
CY8C20160.  
Low operating current  
Active current: continuous sensor scan:1.5 mA  
Sleep current: no scan, continuous sleep:2.6 uA  
The user can configure registers with parameters needed to  
adjust the operation and sensitivity of the CapSense system.  
CY8C20160 supports a standard I²C serial communication  
interface that allows the host to configure the device and to read  
sensor information in real time through easy register access.  
Available in 16-pin COL and 16-pin SOIC packages  
The CapSense Express Core  
The CapSense Express Core has a powerful configuration and  
control block. It encompasses SRAM for data storage, an  
interrupt controller, sleep, and watchdog timers. System  
resources provide additional capability, such as a configurable  
I2C slave communication interface and various system resets.  
The Analog System is composed of the CapSense PSoC block  
which supports capacitive sensing of up to six inputs.  
Cypress Semiconductor Corporation  
Document Number:001-17347 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 11, 2008  
[+] Feedback  

CY8C20160-SX2I 替代型号

型号 品牌 替代类型 描述 数据表
CY8C20180-SX2I CYPRESS

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