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CY7C53120E4-40SXIT PDF预览

CY7C53120E4-40SXIT

更新时间: 2024-11-25 02:51:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 380K
描述
Neuron㈢ Chip Network Processor

CY7C53120E4-40SXIT 数据手册

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CY7C53150  
CY7C53120  
Neuron® Chip Network Processor  
Features  
• Three 8-bit pipelined processors for concurrent processing  
of application code and network traffic  
• 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM  
containing LonTalk® network protocol firmware  
• 11-pin IO port programmable in 34 modes for fast appli-  
cation program development  
• Maximum input clock operation of 20 MHz (CY7C53150),  
10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a  
–40°C to 85°C[2] temperature range  
• Two 16-bit timer/counters for measuring and generating IO  
device waveforms  
• 64-pin TQFP package (CY7C53150)  
• 5-pin communication port that supports direct connect and  
network transceiver interfaces  
• 32-pin SOIC or 44-pin TQFP package (CY7C53120)  
Functional Description  
• Programmable pull ups on IO4–IO7 and 20 mA sink current  
on IO0–IO3  
The CY7C531x0 Neuron® chip implements a node for  
LonWorks® distributed intelligent control networks. It incorpo-  
rates, on a single chip, the necessary communication and  
control functions, both in hardware and firmware, that facilitate  
the design of a LonWorks node.  
• Unique48-bitIDnumberineverydevicetofacilitatenetwork  
installation and management  
• Low operating current; sleep mode operation for reduced  
current consumption[1]  
• 0.35 μm Flash process technology  
• 5.0V operation  
The CY7C531x0 contains a very flexible 5-pin communication  
port that can be configured to interface with a wide variety of  
media transceivers at a wide range of data rates. The most  
common transceiver types are twisted-pair, powerline, RF, IR,  
fiber-optics, and coaxial.  
• On-chip LVD circuit to prevent nonvolatile memory  
corruption during voltage drops  
• 2,048 bytes of SRAM for buffering network data, system,  
and application data storage  
The CY7C531x0 is manufactured using state of the art  
0.35-μm Flash technology, providing to designers the most  
cost-effective Neuron chip solution.  
• 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2),  
4096 bytes (CY7C53120E4) of Flash memory with on-chip  
charge pump for flexible storage of configuration data and  
application code  
Services at every layer of the OSI networking reference model  
are implemented in the LonTalk firmware based protocol  
stored in 10-KB ROM (CY7C53120E2), 12-KB ROM  
(CY7C53120E4), or off-chip memory (CY7C53150). The  
• Addresses up to 58 KB of external memory (CY7C53150)  
Logic Block Diagram  
CP4  
CP0  
Media Access  
Control Processor  
Communications  
Port  
IO10  
IO0  
Network  
Internal  
IO Block  
Processor  
Data Bus  
(0:7)  
Application  
Processor  
2 Timer/  
Counters  
Internal  
Address Bus  
(0:15)  
2 KB RAM  
CLK1  
Oscillator,  
Clock, and  
Control  
CLK2  
SERVICE  
RESET  
Flash  
External  
Address/Data Bus  
(CY7C53150)  
ROM  
(CY7C53120)  
Notes  
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. For details, refer to Cypress’s Neuron  
Metastability Description application note.  
2. Maximum Junction Temperature is 105°C. T  
= T  
+ V•I•θJA. 32-pin SOIC θJA = 51C/W. 44-pin TQFP θJA = 43C/W. 64-pin TQFP θJA = 44C/W.  
Junction  
Ambient  
Cypress Semiconductor Corporation  
Document #: 38-10001 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 14, 2007  
[+] Feedback  

CY7C53120E4-40SXIT 替代型号

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