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CY7C53150L-64AI

更新时间： 2024-11-25 00:00:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		电信集成电路电信电路
页数	文件大小	规格书
14页	497K
描述
3.3V Neuron Chip Network Processor

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CY7C53150L-64AI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64	针数：	64
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.71	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	14 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	64
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.6 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

CY7C53150L-64AI 数据手册

CY7C53120L8

CY7C53150L

3.3V Neuron^®Chip Network Processor

Features

Functional Description

• 3.3V operation

The 3.3V Neuron^chip (CY7C53120L8/3150L) is a low-power

version of the 5V Neuron chip with a number of feature

enhancements. The CY7C53120L8/3150L Neuron chip imple-

ments a device for LonWorks^distributed intelligent control

networks. It incorporates, on a single chip, the necessary

communication and control functions, both in hardware and

firmware, that facilitate the design of a LonWorks device.

• Three 8-bit pipelined processors for concurrent

processing of application code and network traffic

• Hardware UART/SPI interface

• Eleven-pin I/O port programmable in 38 modes for fast

application program development. I/O port is 5V input

tolerant

The CY7C53120L8/3150L supports all the functionality of the

5V CY7C531x0 Neuron chip. Additionally it features 4KBytes

of RAM, 8KBytes of Flash memory (CY7C53120L8), and

hardware UART/SPI. The CY7C53120L8/3150L has an 11-pin

configurable I/O block. The I/Os are all 5V-tolerant to allow

interfacing to TTL Compatible 5V components and microcon-

trollers.

• Two 16-bit timer/counters for measuring and gener-

ating I/O device waveforms

• Five-pin communication port that supports direct

connect and network transceiver interfaces, and

operates at 3.3V or 5V

• Programmable pull-ups on IO4–IO7 and 20-mA sink

current on IO0–IO3

The CY7C53120L8/3150L contains a very flexible five-pin

communication port that can be configured to interface with a

wide variety of media transceivers at a wide range of data

rates. The communication port can operate at either 3.3V or

5V. In 5V mode the communication port is completely

backward compatible with existing 5V transceivers. The most

common transceiver types are twisted-pair, powerline, RF, IR,

fiber-optics, and coaxial.

• Unique 48-bit Neuron ID number in every device to facil-

itate network installation and management

• 0.35-µm Flash process technology

• On-chip LVD circuit with programmable trip point and

digital filter settings

• Programmable Pulse Stretching reset

• 4,096 bytes of SRAM for buffering network data,

system, and application data storage

The CY7C53150L incorporates an external memory interface

that can address up to 56KBytes with 8KBytes of the address

space mapped internally. LonWorks devices that require large

application programs can take advantage of this external

memory capability.

• 2.75 KBytes (CY7C53150L), 8KBytes (CY7C53120L8) of

Flash memory with on-chip charge pump for flexible

storage of configuration data and application code

• Addresses up to 56 KBytes of external memory

(CY7C53150L)

Services at every layer of the OSI networking reference model

are implemented in the LonTalk firmware-based protocol

stored in 16KBytes ROM (CY7C53120L8), or off-chip memory

(CY7C53150L). The firmware also contains 38 prepro-

grammed I/O drivers, simplifying application programming.

The application program is stored in the Flash memory

(CY7C53120L8) and/or off-chip memory (CY7C53150L), and

may be updated by downloading over the network.

• 16 KBytes (CY7C53120L8) of ROM containingLonTalk^

network protocol firmware

• Maximum input clock operation of 20MHz over –40°C

to 85°C^[1]temperature range

• 64-pin TQFP package (CY7C53150L)

• 32-pin SOIC or 44-pin TQFP package (CY7C53120L8)

Logic Block Diagram

CP4

CP0

Communications

Port

Media Access

Control Processor

Network

Internal

Two Timer/Counters

4-pin UART/SPI

Processor

Data Bus

(0:7)

IO10

IO7

Application

Processor

Internal

Address Bus

(0:15)

IO6

I/O Block

4KBytes RAM

Flash

IO0

CLK1

CLK2

Oscillator,

Clock, and

Control

SERVICE

RESET

ROM

(CY7C53120L8)

External Address and

Data Bus (CY7C53150L)

Note:

1. Maximum junction temperature is 105°C. T

= T

+ V•I•θ . 32-pin SOIC θ = 61.07°C/W. 44-pin TQFP θ = 69.5°C/W. 64-pin TQFP θ = 56.15°C/W.

JA JA JA JA

Junction

Ambient

Cypress Semiconductor Corporation

Document #: 38-10002 Rev. *E

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 2, 2004

12 3 4 5 6 7...14

中文翻译

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