Datasheet > CY7C53120E4-40SIT

CY7C53120E4-40SIT

更新时间： 2024-11-25 20:53:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟局域网光电二极管外围集成电路
页数	文件大小	规格书
12页	225K
描述
LAN Controller, 5 Channel(s), CMOS, PDSO32, 0.450 INCH, SOIC-32

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CY7C53120E4-40SIT 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	32
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.82	地址总线宽度：
边界扫描：	NO	最大时钟频率：	40 MHz
数据编码/解码方法：	DIFF BIPHASE-LEVEL	外部数据总线宽度：
JESD-30 代码：	R-PDSO-G32	JESD-609代码：	e0
长度：	20.447 mm	低功率模式：	NO
串行 I/O 数：	5	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.8194 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	11.303 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：	1

CY7C53120E4-40SIT 数据手册

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CY7C53150

CY7C53120

Neuron^®Chip Network Processor

Features

Functional Description

• Three eight-bit pipelined processors for concurrent

processing of application code and network traffic

• 11-pin I/O port programmablein 34 modes for fast appli-

cation program development

• Two 16-bit timer/counters for measuring and gener-

ating I/O device waveforms

• Five-pin communication port that supports direct

connect and network transceiver interfaces

• Programmable pull-ups on IO4–IO7 and 20-mA sink

current on IO0–IO3

• Unique 48-bit ID number in every device to facilitate

network installation and management

The CY7C531x0 Neuron chip implements a node for

LonWorks distributed intelligent control networks. It incorpo-

rates, on a single chip, the necessary communication and

control functions, both in hardware and firmware, that facilitate

the design of a LonWorks node.

The CY7C531x0 contains a very flexible five-pin communi-

cation port that can be configured to interface with a wide

variety of media transceivers at a wide range of data rates. The

most common transceiver types are twisted-pair, powerline,

RF, IR, fiber-optics, and coaxial.

The CY7C531x0 is manufactured using state-of-the-art

0.35-µm Flash technology, providing to designers the most

cost-effective Neuron chip solution.

• Low operating current; sleep mode operation for

reduced current consumption^[1]

Services at every layer of the OSI networking reference model

are implemented in the LonTalk firmware-based protocol

stored in 10-KB ROM (CY7C53120E2), 12-KB ROM

(CY7C53120E4), or off-chip memory (CY7C53150). The

firmware also contains 34 preprogrammed I/O drivers, greatly

simplifying application programming. The application program

is stored in the Flash memory (CY7C53120) and/or off-chip

memory (CY7C53150), and may be updated by downloading

over the network.

• 0.35-µm Flash process technology

• 5.0V operation

• On-chip LVD circuit to prevent nonvolatile memory

corruption during voltage drops

• 2,048 bytes of SRAM for buffering network data,

system, and application data storage

• 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2),

4096 bytes (CY7C53120E4) of Flash memory with

on-chip charge pump for flexible storage of configu-

ration data and application code

• Addresses up to 58 KB of external memory

(CY7C53150)

• 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM

containing LonTalk network protocol firmware

• Maximum input clock operation of 20 MHz

(CY7C53150), 10 MHz (CY7C53120E2), 40 MHz

(CY7C53120E4) over a –40°C to 85°C^[2]temperature

range

The CY7C53150 incorporates an external memory interface

that can address up to 64 KB with 6 KB of the address space

mapped internally. LonWorks nodes that require large appli-

cation programs can take advantage of this external memory

capability.

The CY7C53150 Neuron chip is an exact replacement for the

Motorola MC143150Bx and Toshiba TMPN3150B1 devices.

The CY7C53120E2 Neuron chip is an exact replacement for

the Motorola MC143120E2 device since it contains the same

firmware in ROM.

• 64-pin TQFP package (CY7C53150)

• 32-pin SOIC or 44-pin TQFP package (CY7C53120)

Logic Block Diagram

CP4

CP0

Media Access

Control Processor

Communications

Port

IO10

IO0

Network

Internal

I/O Block

Processor

Data Bus

(0:7)

Application

Processor

2 Timer/

Counters

Internal

Address Bus

(0:15)

2 KB RAM

CLK1

Oscillator,

Clock, and

Control

CLK2

SERVICE

RESET

Flash

External

Address/Data Bus

(CY7C53150)

ROM

(CY7C53120)

Notes:

1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. For details please refer to Cypress’s

Neuron Metastability Description application note.

2. Maximum Junction Temperature is 105°C. T_Junction= T_Ambient+ V•I•θ_JA. 32-pin SOIC θ_JA= 51C/W. 44-pin TQFP θ_JA= 43C/W. 64-pin TQFP θ_JA= 44C/W.

Cypress Semiconductor Corporation

Document #: 38-10001 Rev. *D

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised March 24, 2003

12 3 4 5 6 7...12

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与CY7C53120E4-40SIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C53120E4-40SXI	CYPRESS	获取价格	Neuron㈢ Chip Network Processor
CY7C53120E4-40SXI	INFINEON	获取价格	Control Communications
CY7C53120E4-40SXIT	CYPRESS	获取价格	Neuron㈢ Chip Network Processor
CY7C53120E4-40SXIT	INFINEON	获取价格	Control Communications
CY7C53120L8	CYPRESS	获取价格	3.3V Neuron Chip Network Processor
CY7C53120L8-32SI	CYPRESS	获取价格	3.3V Neuron Chip Network Processor
CY7C53120L8-44AI	CYPRESS	获取价格	3.3V Neuron Chip Network Processor
CY7C53150	CYPRESS	获取价格	Neuron?? Chip Network Processor
CY7C53150_07	CYPRESS	获取价格	Neuron㈢ Chip Network Processor
CY7C53150-20AI	CYPRESS	获取价格	Neuron?? Chip Network Processor

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