Datasheet > 存储 > OTP ROM> CY7C265-50JC

CY7C265-50JC

更新时间： 2024-11-07 13:07:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		可编程只读存储器
页数	文件大小	规格书
11页	316K
描述
OTP ROM, 8KX8, 25ns, CMOS, PQCC28, PLASTIC, LCC-28

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技术参数
数据手册

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CY7C265-50JC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	PLASTIC, LCC-28
针数：	28	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.81	Is Samacsys：	N
最长访问时间：	25 ns	其他特性：	PROGRAMMABLE SYNCHRONOUS OR ASYNCHRONOUS OUTPUT ENABLE; PROGRAMMABLE ASYNCHRONOUS REGISTERS
I/O 类型：	COMMON	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.5316 mm
内存密度：	65536 bit	内存集成电路类型：	OTP ROM
内存宽度：	8	功能数量：	1
端子数量：	28	字数：	8192 words
字数代码：	8000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8KX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	4.572 mm
最大待机电流：	0.08 A	子类别：	OTP ROMs
最大压摆率：	0.08 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	11.5316 mm	Base Number Matches：	1

CY7C265-50JC 数据手册

CY7C265

8K x 8 Registered PROM

If the asynchronous enable (E) is being used, the outputs may

be disabled at any time by switching the enable to a logic

HIGH, and may be returned to the active state by switching the

enable to a logic LOW.

Features

• CMOS for optimum speed/power

• High speed (Commercial)

— 15 ns address set-up

If the synchronous enable (E_S) is being used, the outputs will

go to the OFF or high-impedance state upon the next positive

clock edge after the synchronous enable input is switched to

a HIGH level. If the synchronous enable pin is switched to a

logic LOW, the subsequent positive clock edge will return the

output to the active state. Following a positive clock edge, the

address and synchronous enable inputs are free to change

since no change in the output will occur until the next

LOW-to-HIGH transition of the clock. This unique feature al-

lows the CY7C265 decoders and sense amplifiers to access

the next location while previously addressed data remains sta-

ble on the outputs.

— 12 ns clock to output

• Low power

— 660 mW (Commercial)

• On-chip edge-triggered registers

— Ideal for pipelined microprogrammed systems

• EPROM technology

— 100% programmable

— Reprogrammable (CY7C265W)

• 5V ±10% V_CC, commercial and military

• Capable of withstanding >2001V static discharge

• Slim 28-pin, 300-mil plastic or hermetic DIP

If the E/I pin is used for INIT (asynchronous), then the outputs

are permanently enabled. The initialize function is useful

during power-up and time-out sequences, and can facilitate

implementation of other sophisticated functions such as a

built-in “jump start” address. When activated, the initialize

control input causes the contents of a user programmed

8193rd 8-bit word to be loaded into the on-chip register. Each

bit is programmable and the initialize function can be used to

load any desired combination of 1’s and 0’s into the register.

In the unprogrammed state, activating INIT will generate a

word are programmed to be a 1, activating INIT performs a

Functional Description

The CY7C265 is a 8192 x 8 registered PROM. It is organized

as 8,192 words by 8 bits wide, and has a pipeline output

initialize byte that may be loaded into the pipeline register with

the initialize signal. The programmable initialize byte is the

8,193rd byte in the PROM and its value is programmed at the

time of use.

Packaged in 28 pins, the PROM has 13 address signals (A₀

through A₁₂), 8 data out signals (O₀through O₇), E/I (enable

or initialize), and CLOCK.

Applying a LOW to the INIT input causes an immediate load

of the programmed initialize word into the pipeline register and

onto the outputs. The INIT LOW disables clock and must

return HIGH to enable clock independent of all other inputs,

including the clock.

CLOCK functions as a pipeline clock, loading the contents of

the addressed memory location into the pipeline register on

each rising edge. The data will appear on the outputs if they

are enabled. One pin on the CY7C265 is programmed to

perform either the enable or the initialize function.

Cypress Semiconductor Corporation

Document #: 38-04012 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised October 9, 2002

12 3 4 5 6 7...11

中文翻译

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与CY7C265-50JC相关器件

型号	品牌	获取价格	描述	数据表
CY7C265-50JCR	CYPRESS	获取价格	OTP ROM, 8KX8, 25ns, CMOS, PQCC28, PLASTIC, LCC-28
CY7C265-50JCT	CYPRESS	获取价格	OTP ROM, 8KX8, 25ns, CMOS, PQCC28, PLASTIC, LCC-28
CY7C265-50LC	ETC	获取价格	x8 EPROM
CY7C265-50LMB	ETC	获取价格	EPROM\|8KX8\|CMOS\|LLCC\|28PIN\|CERAMIC
CY7C265-50PI	CYPRESS	获取价格	OTP ROM, 8KX8, 25ns, CMOS, PDIP28, 0.300 INCH, SLIM, PLASTIC, DIP-28
CY7C265-50QC	ETC	获取价格	x8 EPROM
CY7C265-50WMB	CYPRESS	获取价格	UVPROM, 8KX8, 25ns, CMOS, CDIP28, 0.300 INCH, SLIM, HERMETIC SEALED, WINDOWED, CERDIP-28
CY7C265-60DC	ETC	获取价格	x8 EPROM
CY7C265-60JC	ETC	获取价格	x8 EPROM
CY7C265-60JCR	CYPRESS	获取价格	OTP ROM, 8KX8, 25ns, CMOS, PQCC28, PLASTIC, LCC-28

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