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CY7C1472V33-200AXCT PDF预览

CY7C1472V33-200AXCT

更新时间： 2024-11-09 19:54:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
40页 738K
描述
ZBT SRAM, 4MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1472V33-200AXCT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.54
最长访问时间：3 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e3/e4
长度：20 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：100
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1472V33-200AXCT 数据手册

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CY7C1470V33  
CY7C1472V33  
CY7C1474V33  
72-Mbit (2M × 36/4M × 18/1M × 72)  
Pipelined SRAM with NoBL™ Architecture  
72-Mbit (2M  
× 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin compatible and functionally equivalent to ZBT  
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are  
3.3 V, 2M × 36/4M × 18/1M × 72 synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL logic, respectively.  
They are designed to support unlimited true back-to-back  
read/write operations with no wait states. The CY7C1470V33,  
CY7C1472V33, and CY7C1474V33 are equipped with the  
advanced (NoBL) logic required to enable consecutive  
read/write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of data  
in systems that require frequent write/read transitions. The  
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin  
compatible and functionally equivalent to ZBT devices.  
■ Supports 200 MHz Bus operations with zero wait states  
❐ Available speed grades are 200 and 167 MHz  
■ Internally self timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte write capability  
■ Single 3.3 V power supply  
■ 3.3 V/2.5 V I/O power supply  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Fast clock-to-output time  
❐ 3.0 ns (for 200 MHz device)  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self timed writes  
Write operations are controlled by the byte write selects  
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33  
and BWa–BWb for CY7C1472V33) and a write enable (WE)  
input. All writes are conducted with on-chip synchronous self  
timed write circuitry.  
■ CY7C1470V33 available in JEDEC-standard Pb-free 100-pin  
TQFP, and non Pb-free 165-ball FBGA package.  
CY7C1472V33 available in JEDEC-standard Pb-free 100-pin  
TQFP. CY7C1474V33 available in non Pb-free 209-ball FBGA  
package  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tristate control. In order to avoid bus  
contention, the output drivers are synchronously tristated during  
the data portion of a write sequence.  
■ IEEE 1149.1 JTAG boundary scan compatible  
■ Burst capability – linear or interleaved burst order  
■ “ZZ” sleep mode option and stop clock option  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum access time  
200 MHz  
3.0  
167 MHz Unit  
3.4  
450  
120  
ns  
Maximum operating current  
500  
mA  
mA  
Maximum CMOS standby current  
120  
Errata: For information on silicon errata, see Errata on page 35. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-05289 Rev. *X  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 5, 2018  
 
 
 
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CY7C1472V33-200AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1472V33-200AXC CYPRESS

完全替代

 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

与CY7C1472V33-200AXCT相关器件

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CY7C1472V33-200AXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472V33-200BZC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-200BZI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472V33-200BZXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-200BZXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472V33-250AXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-250AXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472V33-250BGC CYPRESS

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 		ZBT SRAM, 4MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1472V33-250BZC CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-250BZI CYPRESS

获取价格

 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

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