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CY7C1473BV25-133AXC PDF预览

CY7C1473BV25-133AXC

更新时间： 2024-11-09 05:19:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 848K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1473BV25-133AXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84最长访问时间：6.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：1.8/2.5,2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.12 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.305 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mm

CY7C1473BV25-133AXC 数据手册

 浏览型号CY7C1473BV25-133AXC的Datasheet PDF文件第2页浏览型号CY7C1473BV25-133AXC的Datasheet PDF文件第3页浏览型号CY7C1473BV25-133AXC的Datasheet PDF文件第4页浏览型号CY7C1473BV25-133AXC的Datasheet PDF文件第5页浏览型号CY7C1473BV25-133AXC的Datasheet PDF文件第6页浏览型号CY7C1473BV25-133AXC的Datasheet PDF文件第7页 
CY7C1471BV25  
CY7C1473BV25, CY7C1475BV25  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Flow-Through SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25  
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through  
burst SRAMs designed specifically to support unlimited true  
back-to-back read or write operations without the insertion of  
wait states. The CY7C1471BV25, CY7C1473BV25, and  
CY7C1475BV25 are equipped with the advanced No Bus  
Latency (NoBL) logic required to enable consecutive read or  
write operations with data transferred on every clock cycle. This  
feature dramatically improves the throughput of data through the  
SRAM, especially in systems that require frequent write-read  
transitions.  
■ Supports up to 133 MHz bus operations with zero wait states  
■ Data transfers on every clock  
■ Pin compatible and functionally equivalent to ZBT™ devices  
■ Internally self timed output buffer control to eliminate the need  
to use OE  
■ Registered inputs for flow through operation  
■ Byte Write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
Clock Enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 6.5 ns (133-MHz device).  
■ 2.5V IO supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 6.5 ns (for 133-MHz device)  
Write operations are controlled by two or four Byte Write Select  
(BWX) and a Write Enable (WE) input. All writes are conducted  
with on-chip synchronous self timed write circuitry.  
■ Clock Enable (CEN) pin to enable clock and suspend operation  
■ Synchronous self timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide easy bank selection  
and output tri-state control. To avoid bus contention, the output  
drivers are synchronously tri-stated during the data portion of a  
write sequence.  
■ Asynchronous Output Enable (OE)  
■ CY7C1471BV25, CY7C1473BV25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1475BV25  
available in Pb-free and non-Pb-free 209-ball FBGA package.  
For best practice recommendations, refer to the Cypress appli-  
cation note AN1064, SRAM System Guidelines.  
■ Three Chip Enables (CE1, CE2, CE3) for simple depth  
expansion.  
■ Automatic power down feature available using ZZ mode or CE  
deselect.  
■ IEEE 1149.1 JTAG Boundary Scan compatible  
■ Burst Capability - linear or interleaved burst order  
■ Low standby power  
Selection Guide  
Description  
Maximum Access Time  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Operating Current  
305  
275  
mA  
mA  
Maximum CMOS Standby Current  
120  
120  
Cypress Semiconductor Corporation  
Document #: 001-15013 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 29, 2008  
[+] Feedback  
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