Datasheet > CY7C1472V33-300BGC

CY7C1472V33-300BGC

更新时间： 2024-09-18 05:04:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
26页	831K
描述
ZBT SRAM, 4MX18, 2.2ns, CMOS, PBGA119

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CY7C1472V33-300BGC 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.8	最长访问时间：	2.2 ns
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B119	内存密度：	75497472 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
端子数量：	119	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
最小待机电流：	3.14 V	子类别：	SRAMs
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
Base Number Matches：	1

CY7C1472V33-300BGC 数据手册

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CY7C1470V33

CY7C1472V33

CY7C1474V33

ADVANCE

INFORMATION

2M x 36/4M x 18/1M x 72 Pipelined SRAM

with NoBL™ Architecture

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

BWS_c, BWS_d, BWS_e, BWS_f, BWS_g, BWS_h), and Read/Write

Features

• Zero Bus Latency™, no dead cycles between Write and

Read cycles

• Fast clock speed: 300, 250, 200, and 167 MHz

• Fast access time: 2.2, 2.4, 3.0 and 3.4 ns

• Internally synchronized registered outputs eliminate

the need to control OE

control (WE). BWS_cand BWS_dapply to CY7C1470V33 and

CY7C1472V33 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1474V33 only.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later its associated data

occurs, either Read or Write.

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Single WE (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

A Clock Enable (CEN) pin allows operation of the

CY7C1470V33, CY7C1472V33, and CY7C1474V33 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is HIGH; the internal device registers will

hold their previous values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three is not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in a

high-impedance state two cycles after chip is deselected or a

Write cycle is initiated.

• Interleaved or linear four-word burst capability

• Individualbytewrite(BWS_a–BWS_h)control(maybetied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1470V33 and CY7C1472V33). 209-ball

FBGA package for CY7C1474V33.

The CY7C1470V33, CY7C1472V33, and CY7C1474V33

have an on-chip two-bit burst counter. In burst mode,

CY7C1470V33, CY7C1472V33, and CY7C1474V33 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH)

Functional Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33

SRAMs are designed to eliminate dead cycles when making

transitions from Read to Write or vice versa. These SRAMs are

optimized for 100% bus utilization and achieve Zero Bus

Latency. They integrate 2,097,152 × 36/4,194,304 × 18/

1,048,576 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Cypress Synchronous Burst

SRAM family employs high-speed, low-power CMOS designs

using advanced single-layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and Write

LOGIC

2M × 36/

4M × 18/

1M × 72

BWS

MEMORY

ARRAY

BWS

X = 20:0 X=a,b,c,d X=a,b,c,d X=a,b,c,d

2M × 36

Mode

X = 21:0

X = 19:0

X = a, b

X = a, b X = a, b

4M × 18

1M × 72

X = a, b

X = a, b,

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05289 Rev. **

Revised August 2, 2002

12 3 4 5 6 7...26

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与CY7C1472V33-300BGC相关器件

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CY7C1472V33-300BZC	CYPRESS	获取价格	ZBT SRAM, 4MX18, 2.2ns, CMOS, PBGA165
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CY7C1473BV25	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1473BV25-100AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
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