Datasheet > CY7C1473BV33

CY7C1473BV33

更新时间： 2024-11-09 06:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	884K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1473BV33 数据手册

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through

SRAM with NoBL™ Architecture

Features

Functional Description

■ No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33

are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through

burst SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471BV33, CY7C1473BV33, and

CY7C1475BV33 are equipped with the advanced No Bus

Latency (NoBL) logic. NoBL™ is required to enable consecutive

read or write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.

■ Supports up to 133 MHz bus operations with zero wait states

■ Data is transferred on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow through operation

■ Byte Write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

■ 3.3V/2.5V IO supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133 MHz device)

Write operations are controlled by two or four Byte Write Select

(BW_X) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

■ Clock Enable (CEN) pin to enable clock and suspend operation

■ Synchronous self-timed writes

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence. For best practice recommendations,

refer to the Cypress application note AN1064 “SRAM System

Guidelines”.

■ Asynchronous Output Enable (OE)

■ CY7C1471BV33, CY7C1473BV33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-Ball FBGA package. CY7C1475BV33

available in Pb-free and non-Pb-free 209-Ball FBGA package

■ Three Chip Enables (CE₁, CE₂, CE₃) for simple depth

expansion

■ Automatic power down feature available using ZZ mode or CE

deselect

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst Capability—linear or interleaved burst order

■ Low standby power

Selection Guide

Description

Maximum Access Time

133 MHz

6.5

117 MHz

8.5

Unit

Maximum Operating Current

Maximum CMOS Standby Current

305

275

120

Cypress Semiconductor Corporation

Document #: 001-15029 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 05, 2008

[+] Feedback

12 3 4 5 6 7...32

中文翻译

下载PDF

与CY7C1473BV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1473BV33-117AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-117AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-117BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-117BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-117BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-117BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-133AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-133AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-133BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473BV33-133BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

与CY7C1473BV33相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

48
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1473BV33

CY7C1473BV33 数据手册

与CY7C1473BV33相关器件

与CY7C1473BV33相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1473BV33

CY7C1473BV33 数据手册

与CY7C1473BV33相关器件

与CY7C1473BV33相关文章

您还可以找

您在本页遇到什么问题？