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CY7C1472V33-167BZXC PDF预览

CY7C1472V33-167BZXC

更新时间： 2024-11-06 22:36:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
28页 379K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

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CY7C1472V33-167BZXC 数据手册

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CY7C1470V33  
CY7C1472V33  
CY7C1474V33  
PRELIMINARY  
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined  
SRAM with NoBL™ Architecture  
Features  
Functional Description  
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200, and 167 MHz  
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back  
Read/Write operations with no wait states. The  
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are  
equipped with the advanced (NoBL) logic required to enable  
consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent  
Write/Read transitions. The CY7C1470V33, CY7C1472V33,  
and CY7C1474V33 are pin compatible and functionally equiv-  
alent to ZBT devices.  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 3.3V power supply  
• 3.3V/2.5V I/O power supply  
• Fast clock-to-output time  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
— 3.0 ns (for 250-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33  
and BWa–BWb for CY7C1472V33) and a Write Enable (WE)  
input. All writes are conducted with on-chip synchronous  
self-timed write circuitry.  
• CY7C1470V33 and CY7C1472V33 available in lead-free  
100 TQFP, and 165-ball fBGA packages. CY7C1474V33  
available in 209-ball fBGA package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• IEEE 1149.1 JTAG Boundary Scan compatible  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram-CY7C1470V33 (2M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05289 Rev. *E  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 23, 2004  
1234567...28

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CY7C1472V33-200BZXC CYPRESS

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