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CY7C1472V25-200BZC

更新时间： 2024-11-06 22:36:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 383K
描述
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1472V25-200BZC 数据手册

 浏览型号CY7C1472V25-200BZC的Datasheet PDF文件第2页浏览型号CY7C1472V25-200BZC的Datasheet PDF文件第3页浏览型号CY7C1472V25-200BZC的Datasheet PDF文件第4页浏览型号CY7C1472V25-200BZC的Datasheet PDF文件第5页浏览型号CY7C1472V25-200BZC的Datasheet PDF文件第6页浏览型号CY7C1472V25-200BZC的Datasheet PDF文件第7页 
CY7C1470V25  
CY7C1472V25  
CY7C1474V25  
PRELIMINARY  
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined  
SRAM with NoBL™ Architecture  
Functional Description  
Features  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200, and 167 MHz  
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,  
2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs  
with No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations with no wait states. The CY7C1470V25/  
CY7C1472V25/CY7C1474V25 are equipped with the  
advanced (NoBL) logic required to enable consecutive  
Read/Write operations with data being transferred on every  
clock cycle. This feature dramatically improves the throughput  
of data in systems that require frequent Write/Read transitions.  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
The  
CY7C1470V25/CY7C1472V25/CY7C1474V25  
are  
• Single 2.5V power supply  
pin-compatible and functionally equivalent to ZBT devices.  
• 2.5V/1.8V I/O operation  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle. Write operations are controlled by the  
Byte Write Selects (BWa–BWh for CY7C1474V25, BWa–BWd  
for CY7C1470V25 and BWa–BWb for CY7C1472V25) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
• Fast clock-to-output times  
— 3.0 ns (for 250-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• CY7C1470V25 and CY7C1472V25 available in lead-free  
100 TQFP, and 165 fBGA packages. CY7C1474V25  
available in 209-ball fBGA package.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
• Compatible with IEEE 1149.1 JTAG Boundary Scan  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram-CY7C1470V25 (2M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
D1  
D0  
Q1  
Q0  
A0'  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05290 Rev. *E  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised December 5, 2004  
1234567...27

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