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CY7C1472V25-200BZXI PDF预览

CY7C1472V25-200BZXI

更新时间： 2024-09-17 05:19:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
28页 512K
描述
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1472V25-200BZXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.53
Is Samacsys：N最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：17 mm
内存密度：75497472 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：1.8/2.5,2.5 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：2.38 V
子类别：SRAMs最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：15 mmBase Number Matches：1

CY7C1472V25-200BZXI 数据手册

 浏览型号CY7C1472V25-200BZXI的Datasheet PDF文件第2页浏览型号CY7C1472V25-200BZXI的Datasheet PDF文件第3页浏览型号CY7C1472V25-200BZXI的Datasheet PDF文件第4页浏览型号CY7C1472V25-200BZXI的Datasheet PDF文件第5页浏览型号CY7C1472V25-200BZXI的Datasheet PDF文件第6页浏览型号CY7C1472V25-200BZXI的Datasheet PDF文件第7页 
CY7C1470V25  
CY7C1472V25  
CY7C1474V25  
72-Mbit(2M x 36/4M x 18/1M x 72)  
Pipelined SRAM with NoBL™ Architecture  
Functional Description  
Features  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200 and 167 MHz  
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,  
2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs  
with No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations  
with  
no  
wait  
states.  
The  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped  
with the advanced (NoBL) logic required to enable consec-  
utive Read/Write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of data in systems that require frequent Write/Read  
transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25  
are pin-compatible and functionally equivalent to ZBT devices.  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 2.5V power supply  
• 2.5V/1.8V I/O supply (VDDQ  
• Fast clock-to-output times  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle. Write operations are controlled by the  
Byte Write Selects (BWa–BWh for CY7C1474V25, BWa–BWd  
for CY7C1470V25 and BWa–BWb for CY7C1472V25) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
— 3.0 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• CY7C1470V25, CY7C1472V25 available in  
JEDEC-standard lead-free 100-pin TQFP, lead-free and  
non-lead-free 165-ball FBGA package. CY7C1474V25  
available in lead-free and non-lead-free 209 ball FBGA  
package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• IEEE 1149.1 JTAG Boundary Scan compatible  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram-CY7C1470V25 (2M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
D1  
D0  
Q1  
Q0  
A0'  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05290 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 21, 2006  
[+] Feedback  
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中文翻译

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V33 CYPRESS

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CY7C1472V33-167AXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
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