Datasheet > CY7C1472V25-250AC

CY7C1472V25-250AC

更新时间： 2024-11-08 07:55:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	474K
描述
ZBT SRAM, 4MX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1472V25-250AC 数据手册

浏览型号CY7C1472V25-250AC的Datasheet PDF文件第2页

浏览型号CY7C1472V25-250AC的Datasheet PDF文件第3页

浏览型号CY7C1472V25-250AC的Datasheet PDF文件第4页

浏览型号CY7C1472V25-250AC的Datasheet PDF文件第5页

浏览型号CY7C1472V25-250AC的Datasheet PDF文件第6页

浏览型号CY7C1472V25-250AC的Datasheet PDF文件第7页

CY7C1470V25

CY7C1472V25

CY7C1474V25

PRELIMINARY

2M x 36/4M x 18/1M x 72 Pipelined SRAM

with NoBL™ Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

BWS_c, BWS_d, BWS_e, BWS_f, BWS_g, BWS_h), and Read-Write

control (WE). BWS_cand BWS_dapply to CY7C1470V25 and

CY7C1474V25 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1474V25 only.

Features

• Zero Bus Latency™, no dead cycles between Write and

Read cycles

• Fast clock speed: 250, 200, and 167 MHz

• Fast access time: 2.6, 3.0, and 3.4 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later its associated data

occurs, either Read or Write.

• Single 2.5V + 5%/–5%

• Separate V_DDQfor 2.5V or 1.8V I/O

• Single WE (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

Clock Enable (CEN) pin allows operation of the

CY7C1470V25, CY7C1472V25, and CY7C1474V25 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is HIGH and the internal device registers

will hold their previous values.

• Individual byte Write (BWS_a–BWS_h) control (may be

tied LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1470V25 and CY7C1472V25). 209-ball

BGA package for CY7C1474V25.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in high

impedance state two cycles after chip is deselected or a write

cycle is initiated.

• 165-ball FBGA package is offered by opportunity basis

(Please contact Cypress sales or marketing)

The CY7C1470V25, CY7C1472V25, and CY7C1474V25

have an on-chip two-bit burst counter. In the burst mode,

CY7C1470V25, CY7C1472V25, and CY7C1474V25 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH).

Functional Description

The CY7C1470V25, CY7C1472V25, and CY7C1474V25

SRAMs are designed to eliminate dead cycles when transi-

tions from Read to Write or vice versa. These SRAMs are

optimized for 100% bus utilization and achieve Zero Bus

Latency. They integrate 2,097,152 × 36/4,194,304 × 18/

1,048,576 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Cypress Synchronous Burst

SRAM family employs high-speed, low-power CMOS designs

using advanced single layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Cypress Semiconductor Corporation

Document #: 38-05290 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 22, 2003

12 3 4 5 6 7...28

中文翻译

下载PDF

与CY7C1472V25-250AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1472V25-250AXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-250AXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-250BZC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-250BZI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-250BZXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-250BZXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V33	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-167AXCT	CYPRESS	获取价格	ZBT SRAM, 4MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-
CY7C1472V33-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

与CY7C1472V25-250AC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

16
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

14
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

37
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

35

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1472V25-250AC

CY7C1472V25-250AC 数据手册

与CY7C1472V25-250AC相关器件

与CY7C1472V25-250AC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1472V25-250AC

CY7C1472V25-250AC 数据手册

与CY7C1472V25-250AC相关器件

与CY7C1472V25-250AC相关文章

您还可以找

您在本页遇到什么问题？