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CY7C1472BV33-250AXC

更新时间： 2024-11-07 05:19:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	902K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back read

or write operations with no wait states. The CY7C1470BV33,

CY7C1472BV33, and CY7C1474BV33 are equipped with the

advanced (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock cycle.

This feature dramatically improves the throughput of data in

systems that require frequent read or write transitions. The

CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin

compatible and functionally equivalent to ZBT devices.

■ Pin-compatible and functionally equivalent to ZBT™

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ Single 3.3V power supply

■ 3.3V/2.5V IO power supply

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

■ Fast clock-to-output time

❐ 3.0 ns (for 250-MHz device)

■ Clock Enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

Write operations are controlled by the Byte Write Selects

■ CY7C1470BV33, CY7C1472BV33 available in

(BW_a–BW_d

for

CY7C1470BV33,

BW_a–BW_b

for

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1474BV33

available in Pb-free and non-Pb-free 209-ball FBGA package

CY7C1472BV33, and BW_a–BW_hfor CY7C1474BV33) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst capability—linear or interleaved burst order

■ “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

Description

Maximum Access Time

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

3.0

500

120

Maximum Operating Current

500

450

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document #: 001-15031 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 29, 2008

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与CY7C1472BV33-250AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1472BV33-250AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472BV33-250BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1472V25	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-167AC	CYPRESS	获取价格	ZBT SRAM, 4MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1472V25-167AXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1472V25-167AXCT	CYPRESS	获取价格	ZBT SRAM, 4MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-
CY7C1472V25-167AXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR

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