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CY7C1465AV25-100BGI PDF预览

CY7C1465AV25-100BGI

更新时间： 2024-11-16 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
29页 460K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL⑩ Architecture

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CY7C1465AV25-100BGI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：14 X 22 MM, 1.76 MM HEIGHT, FBGA-209针数：209
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
JESD-609代码：e0长度：22 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：72湿度敏感等级：3
功能数量：1端子数量：209
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX72
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA209,11X19,40
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：1.8/2.5,2.5 V认证状态：Not Qualified
座面最大高度：1.96 mm最大待机电流：0.12 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.25 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C1465AV25-100BGI 数据手册

 浏览型号CY7C1465AV25-100BGI的Datasheet PDF文件第2页浏览型号CY7C1465AV25-100BGI的Datasheet PDF文件第3页浏览型号CY7C1465AV25-100BGI的Datasheet PDF文件第4页浏览型号CY7C1465AV25-100BGI的Datasheet PDF文件第5页浏览型号CY7C1465AV25-100BGI的Datasheet PDF文件第6页浏览型号CY7C1465AV25-100BGI的Datasheet PDF文件第7页 
CY7C1461AV25  
CY7C1463AV25  
CY7C1465AV25  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Flow-Through SRAM with NoBL™ Architecture  
Functional Description[1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates  
dead cycles between write and read cycles  
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are  
2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through  
Burst SRAMs designed specifically to support unlimited true  
back-to-back Read/Write operations without the insertion of  
• Can support up to 133-MHz bus operations with zero  
wait states  
wait  
states.  
The  
CY7C1461AV25/CY7C1463AV25/  
— Data is transferred on every clock  
CY7C1465AV25 is equipped with the advanced No Bus  
Latency (NoBL) logic required to enable consecutive  
Read/Write operations with data being transferred on every  
clock cycle. This feature dramatically improves the throughput  
of data through the SRAM, especially in systems that require  
frequent Write-Read transitions.  
• Pin-compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• 2.5V/1.8V I/O power supply  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
Write operations are controlled by the two or four Byte Write  
Select (BWX) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• CY7C1461AV25, CY7C1463AV25 available in  
JEDEC-standard lead-free 100-pin TQFP package,  
lead-free and non-lead-free 165-ball FBGA package.  
CY7C1465AV25 available in lead-free and non-lead-free  
209-ball FBGA package.  
• Three chip enables for simple depth expansion  
• Automatic Power-down feature available using ZZ  
mode or CE deselect  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
270  
250  
mA  
mA  
120  
120  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05355 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 22, 2006  
1234567...29

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