Datasheet > CY7C1470BV25-167AXCT

CY7C1470BV25-167AXCT

更新时间： 2024-11-17 15:17:03

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
29页	893K
描述
Synchronous SRAM

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CY7C1470BV25

CY7C1472BV25

72-Mbit (2M × 36/4M × 18)

Pipelined SRAM with NoBL™ Architecture

72-Mbit (2M

× 36/4M × 18) Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin-compatible and functionally equivalent to ZBT™

The CY7C1470BV25 and CY7C1472BV25 are 2.5 V,

2M × 36/4M × 18 synchronous pipelined burst SRAMs with No

Bus Latency™ (NoBL™) logic, respectively. They are designed

to support unlimited true back-to-back read or write operations

with no wait states. The CY7C1470BV25 and CY7C1472BV25

are equipped with the advanced (NoBL) logic required to enable

consecutive read or write operations with data being transferred

on every clock cycle. This feature dramatically improves the

throughput of data in systems that require frequent read or write

transitions. The CY7C1470BV25 and CY7C1472BV25 are

pin-compatible and functionally equivalent to ZBT devices.

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ Single 2.5 V power supply

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the Byte Write Selects

(BW_a–BW_dfor CY7C1470BV25 and BW_a–BW_bfor

CY7C1472BV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

■ 2.5 V I/O supply (V_DDQ

)

■ Fast clock-to-output times

❐ 3.0 ns (for 250-MHz device)

■ Clock Enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

■ CY7C1470BV25 available in JEDEC-standard Pb-free 100-pin

TQFP and Pb-free 165-ball FBGA package. CY7C1472BV25

available in JEDEC-standard Pb-free 100-pin TQFP

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst capability – linear or interleaved burst order

■ “ZZ” Sleep Mode option and Stop Clock option

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum Access Time

250 MHz

3.0

200 MHz

3.0

167 MHz Unit

3.4

400

120

Maximum Operating Current

450

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document Number: 001-15032 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 7, 2018

12 3 4 5 6 7...29

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与CY7C1470BV25-167AXCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1470BV25-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-167BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-167BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-167BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-167BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-167BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C1470BV25-200AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-200AXC	INFINEON	获取价格	Synchronous SRAM
CY7C1470BV25-200AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV25-200BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

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