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CY7C1470BV33-167AXCT PDF预览

CY7C1470BV33-167AXCT

更新时间： 2024-11-16 19:54:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
40页 738K
描述
ZBT SRAM, 2MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

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CY7C1470BV33-167AXCT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：LQFP, QFP100,.63X.87
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.47
最长访问时间：3.4 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：167 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.45 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

CY7C1470BV33-167AXCT 数据手册

 浏览型号CY7C1470BV33-167AXCT的Datasheet PDF文件第2页浏览型号CY7C1470BV33-167AXCT的Datasheet PDF文件第3页浏览型号CY7C1470BV33-167AXCT的Datasheet PDF文件第4页浏览型号CY7C1470BV33-167AXCT的Datasheet PDF文件第5页浏览型号CY7C1470BV33-167AXCT的Datasheet PDF文件第6页浏览型号CY7C1470BV33-167AXCT的Datasheet PDF文件第7页 
CY7C1470V33  
CY7C1472V33  
CY7C1474V33  
72-Mbit (2M × 36/4M × 18/1M × 72)  
Pipelined SRAM with NoBL™ Architecture  
72-Mbit (2M  
× 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin compatible and functionally equivalent to ZBT  
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are  
3.3 V, 2M × 36/4M × 18/1M × 72 synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL logic, respectively.  
They are designed to support unlimited true back-to-back  
read/write operations with no wait states. The CY7C1470V33,  
CY7C1472V33, and CY7C1474V33 are equipped with the  
advanced (NoBL) logic required to enable consecutive  
read/write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of data  
in systems that require frequent write/read transitions. The  
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin  
compatible and functionally equivalent to ZBT devices.  
■ Supports 200 MHz Bus operations with zero wait states  
❐ Available speed grades are 200 and 167 MHz  
■ Internally self timed output buffer control to eliminate the need  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte write capability  
■ Single 3.3 V power supply  
■ 3.3 V/2.5 V I/O power supply  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Fast clock-to-output time  
❐ 3.0 ns (for 200 MHz device)  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self timed writes  
Write operations are controlled by the byte write selects  
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33  
and BWa–BWb for CY7C1472V33) and a write enable (WE)  
input. All writes are conducted with on-chip synchronous self  
timed write circuitry.  
■ CY7C1470V33 available in JEDEC-standard Pb-free 100-pin  
TQFP, and non Pb-free 165-ball FBGA package.  
CY7C1472V33 available in JEDEC-standard Pb-free 100-pin  
TQFP. CY7C1474V33 available in non Pb-free 209-ball FBGA  
package  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tristate control. In order to avoid bus  
contention, the output drivers are synchronously tristated during  
the data portion of a write sequence.  
■ IEEE 1149.1 JTAG boundary scan compatible  
■ Burst capability – linear or interleaved burst order  
■ “ZZ” sleep mode option and stop clock option  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum access time  
200 MHz  
3.0  
167 MHz Unit  
3.4  
450  
120  
ns  
Maximum operating current  
500  
mA  
mA  
Maximum CMOS standby current  
120  
Errata: For information on silicon errata, see Errata on page 35. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-05289 Rev. *X  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 5, 2018  
 
 
 
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CY7C1470BV33-167AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1470BV33-167AXC CYPRESS

完全替代

 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

与CY7C1470BV33-167AXCT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1470BV33-167AXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-167AXI INFINEON

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 		Synchronous SRAM
CY7C1470BV33-167BZC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-167BZCT CYPRESS

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 		暂无描述
CY7C1470BV33-167BZI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-167BZI INFINEON

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 		Synchronous SRAM
CY7C1470BV33-167BZIT CYPRESS

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 		ZBT SRAM, 2MX36, 3.4ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1470BV33-167BZIT INFINEON

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 		Synchronous SRAM
CY7C1470BV33-167BZXC CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-167BZXI CYPRESS

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 		72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S

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