Datasheet > CY7C1470V25_12

CY7C1470V25_12

更新时间： 2024-11-16 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
38页	854K
描述
72-Mbit (2 M Ã 36/4 M Ã 18/1 M Ã 72) Pipelined SRAM with NoBLâ¢ Architecture

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CY7C1470V25_12 数据手册

CY7C1470V25

CY7C1472V25

CY7C1474V25

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

Pipelined SRAM with NoBL™ Architecture

72-Mbit (2

M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL^TMArchitecture

Features

Functional Description

■ Pin-compatible and functionally equivalent to ZBT™

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V,

2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs

with No Bus Latency™ (NoBL logic, respectively. They are

designed to support unlimited true back-to-back read/write

■ Supports 200-MHz bus operations with zero wait states

❐ Available speed grades are 200 and 167 MHz

operations

with

wait

states.

The

■ Internally self-timed output buffer control to eliminate the need

CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped

with the advanced (NoBL) logic required to enable consecutive

read/write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of data

in systems that require frequent write/read transitions. The

CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible

and functionally equivalent to ZBT devices.

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte write capability

■ Single 2.5 V power supply

■ 2.5 V/1.8 V I/O supply (V_DDQ

)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the Byte Write Selects

(BW_a–BW_hfor CY7C1474V25, BW_a–BW_dfor CY7C1470V25

and BW_a–BW_bfor CY7C1472V25) and a write enable (WE)

input. All writes are conducted with on-chip synchronous

self-timed write circuitry.

■ Fast clock-to-output times

❐ 3.0 ns (for 200-MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

■ CY7C1470V25 available in JEDEC-standard Pb-free 100-pin

TQFP, Pb-free and non Pb-free 165-ball FBGA package.

CY7C1472V25 available in JEDEC-standard Pb-free 100-pin

TQFP. CY7C1474V25 available in Pb-free and non Pb-free

209-ball FBGA package

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated during

the data portion of a write sequence.

■ IEEE 1149.1 JTAG boundary scan compatible

■ Burst capability – linear or interleaved burst order

■ “ZZ” sleep mode option and stop clock option

Selection Guide

Description

Maximum access time

200 MHz

3.0

167 MHz Unit

3.4

400

120

Maximum operating current

450

Maximum CMOS standby current

120

Cypress Semiconductor Corporation

Document Number: 38-05290 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 6, 2012

12 3 4 5 6 7...38

中文翻译

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与CY7C1470V25_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1470V25_13	CYPRESS	获取价格	null72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipe
CY7C1470V25-167AXC	ROCHESTER	获取价格	2MX36 ZBT SRAM, 3.4ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQ
CY7C1470V25-167AXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-167AXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-167BGC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1470V25-167BZC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-167BZI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-167BZXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-167BZXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-200AC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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