Datasheet > CY7C1470V25-250BZI

CY7C1470V25-250BZI

更新时间： 2024-11-16 05:19:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	512K
描述
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1470V25-250BZI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.83	最长访问时间：	3 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2MX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	2.38 V
子类别：	SRAMs	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm

CY7C1470V25-250BZI 数据手册

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CY7C1470V25

CY7C1472V25

CY7C1474V25

72-Mbit(2M x 36/4M x 18/1M x 72)

Pipelined SRAM with NoBL™ Architecture

Functional Description

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,

2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs

with No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations

with

wait

states.

The

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped

with the advanced (NoBL) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of data in systems that require frequent Write/Read

transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25

are pin-compatible and functionally equivalent to ZBT devices.

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply

• 2.5V/1.8V I/O supply (V_DDQ

• Fast clock-to-output times

)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle. Write operations are controlled by the

Byte Write Selects (BW_a–BW_hfor CY7C1474V25, BW_a–BW_d

for CY7C1470V25 and BW_a–BW_bfor CY7C1472V25) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

— 3.0 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• CY7C1470V25, CY7C1472V25 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1474V25

available in lead-free and non-lead-free 209 ball FBGA

package

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Logic Block Diagram-CY7C1470V25 (2M x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05290 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 21, 2006

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与CY7C1470V25-250BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1470V25-250BZXC	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-250BZXI	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V33	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1470V33_06	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470V33_13	CYPRESS	获取价格	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipeline
CY7C1470V33-167AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1470V33-167AXC	INFINEON	获取价格	Synchronous SRAM
CY7C1470V33-167AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1470V33-167AXI	INFINEON	获取价格	Synchronous SRAM
CY7C1470V33-167AXIT	CYPRESS	获取价格	ZBT SRAM, 2MX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-

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