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CY7C1470V25-200AC PDF预览

CY7C1470V25-200AC

更新时间： 2024-11-16 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
38页 854K
描述
ZBT SRAM, 2MX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1470V25-200AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.52最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：1.8/2.5,2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最小待机电流：2.38 V子类别：SRAMs
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1470V25-200AC 数据手册

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CY7C1470V25  
CY7C1472V25  
CY7C1474V25  
72-Mbit (2 M × 36/4 M × 18/1 M × 72)  
Pipelined SRAM with NoBL™ Architecture  
72-Mbit (2  
M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture  
Features  
Functional Description  
■ Pin-compatible and functionally equivalent to ZBT™  
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V,  
2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs  
with No Bus Latency™ (NoBL logic, respectively. They are  
designed to support unlimited true back-to-back read/write  
■ Supports 200-MHz bus operations with zero wait states  
❐ Available speed grades are 200 and 167 MHz  
operations  
with  
no  
wait  
states.  
The  
■ Internally self-timed output buffer control to eliminate the need  
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped  
with the advanced (NoBL) logic required to enable consecutive  
read/write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of data  
in systems that require frequent write/read transitions. The  
CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible  
and functionally equivalent to ZBT devices.  
to use asynchronous OE  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte write capability  
■ Single 2.5 V power supply  
■ 2.5 V/1.8 V I/O supply (VDDQ  
)
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle. Write operations are controlled by the Byte Write Selects  
(BWa–BWh for CY7C1474V25, BWa–BWd for CY7C1470V25  
and BWa–BWb for CY7C1472V25) and a write enable (WE)  
input. All writes are conducted with on-chip synchronous  
self-timed write circuitry.  
■ Fast clock-to-output times  
❐ 3.0 ns (for 200-MHz device)  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
■ CY7C1470V25 available in JEDEC-standard Pb-free 100-pin  
TQFP, Pb-free and non Pb-free 165-ball FBGA package.  
CY7C1472V25 available in JEDEC-standard Pb-free 100-pin  
TQFP. CY7C1474V25 available in Pb-free and non Pb-free  
209-ball FBGA package  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated during  
the data portion of a write sequence.  
■ IEEE 1149.1 JTAG boundary scan compatible  
■ Burst capability – linear or interleaved burst order  
■ “ZZ” sleep mode option and stop clock option  
Selection Guide  
Description  
Maximum access time  
200 MHz  
3.0  
167 MHz Unit  
3.4  
400  
120  
ns  
Maximum operating current  
450  
mA  
mA  
Maximum CMOS standby current  
120  
Cypress Semiconductor Corporation  
Document Number: 38-05290 Rev. *O  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 6, 2012  
1234567...38

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与CY7C1470V25-200AC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1470V25-200AXC CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-200AXC INFINEON

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 		Synchronous SRAM
CY7C1470V25-200AXI CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-200BZC CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-200BZI CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-200BZI INFINEON

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 		Synchronous SRAM
CY7C1470V25-200BZIT CYPRESS

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 		ZBT SRAM, 2MX36, 3ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1470V25-200BZIT INFINEON

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 		Synchronous SRAM
CY7C1470V25-200BZXC CYPRESS

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 		72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25-200BZXC INFINEON

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 		Synchronous SRAM

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