Datasheet > CY7C1470BV33-200BZCT

CY7C1470BV33-200BZCT

更新时间： 2024-11-16 19:24:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
34页	845K
描述
ZBT SRAM, 2MX36, 3ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, , FBGA-165

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技术参数
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CY7C1470BV33-200BZCT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, , FBGA-165	Reach Compliance Code：	not_compliant
风险等级：	5.48	最长访问时间：	3 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.5 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

CY7C1470BV33-200BZCT 数据手册

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CY7C1470BV33

CY7C1472BV33

CY7C1474BV33

72-Mbit (2 M × 36/4 M × 18/1 M × 72)

Pipelined SRAM with NoBL™ Architecture

72-Mbit (2

M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin-compatible and functionally equivalent to ZBT™

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 Synchronous pipelined

burst SRAMs with No Bus Latency™ (NoBL logic,

respectively. They are designed to support unlimited true

back-to-back read or write operations with no wait states. The

CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are

equipped with the advanced (NoBL) logic required to enable

consecutive read or write operations with data being transferred

on every clock cycle. This feature dramatically improves the

throughput of data in systems that require frequent read or write

transitions. The CY7C1470BV33, CY7C1472BV33, and

CY7C1474BV33 are pin compatible and functionally equivalent

to ZBT devices.

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

■ Internally self timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ Single 3.3 V power supply

■ 3.3 V/2.5 V I/O power supply

■ Fast clock-to-output time

❐ 3.0 ns (for 250 MHz device)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

■ Clock Enable (CEN) pin to suspend operation

■ Synchronous self timed writes

■ CY7C1470BV33,

CY7C1472BV33

available

Write operations are controlled by the Byte Write Selects

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1474BV33

available in Pb-free and non-Pb-free 209-ball FBGA package

(BW_a–BW_d

for

CY7C1470BV33,

BW_a–BW_b

for

CY7C1472BV33, and BW_a–BW_hfor CY7C1474BV33) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self timed write circuitry.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst capability – linear or interleaved burst order

■ “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum Access Time

250 MHz

3.0

200 MHz

3.0

167 MHz Unit

3.4

450

120

Maximum Operating Current

500

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document Number: 001-15031 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 20, 2014

12 3 4 5 6 7...34

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与CY7C1470BV33-200BZCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1470BV33-200BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-200BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-200BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-200BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C1470BV33-250AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZXC	INFINEON	获取价格	Synchronous SRAM

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