Datasheet > 存储 > SRAM> CY7C1470BV33-250AXI

CY7C1470BV33-250AXI

更新时间： 2024-11-16 05:19:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
30页	902K
描述
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1470BV33-250AXI 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.5	Is Samacsys：	N
最长访问时间：	3 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	75497472 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.5 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	14 mm	Base Number Matches：	1

CY7C1470BV33-250AXI 数据手册

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back read

or write operations with no wait states. The CY7C1470BV33,

CY7C1472BV33, and CY7C1474BV33 are equipped with the

advanced (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock cycle.

This feature dramatically improves the throughput of data in

systems that require frequent read or write transitions. The

CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin

compatible and functionally equivalent to ZBT devices.

■ Pin-compatible and functionally equivalent to ZBT™

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ Single 3.3V power supply

■ 3.3V/2.5V IO power supply

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

■ Fast clock-to-output time

❐ 3.0 ns (for 250-MHz device)

■ Clock Enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

Write operations are controlled by the Byte Write Selects

■ CY7C1470BV33, CY7C1472BV33 available in

(BW_a–BW_d

for

CY7C1470BV33,

BW_a–BW_b

for

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1474BV33

available in Pb-free and non-Pb-free 209-ball FBGA package

CY7C1472BV33, and BW_a–BW_hfor CY7C1474BV33) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst capability—linear or interleaved burst order

■ “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

Description

Maximum Access Time

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

3.0

500

120

Maximum Operating Current

500

450

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document #: 001-15031 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 29, 2008

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与CY7C1470BV33-250AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1470BV33-250BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470BV33-250BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1470BV33-250BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined S
CY7C1470V25	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25_06	CYPRESS	获取价格	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SR
CY7C1470V25_11	CYPRESS	获取价格	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
CY7C1470V25_12	CYPRESS	获取价格	72-Mbit (2 M Ã 36/4 M Ã 18/1 M Ã 72) Pipel
CY7C1470V25_13	CYPRESS	获取价格	null72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipe

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