Datasheet > 存储 > SRAM> CY7C1464AV33-200BGI

CY7C1464AV33-200BGI

更新时间： 2024-11-16 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
27页	509K
描述
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1464AV33-200BGI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
针数：	209	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	3.2 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B209	JESD-609代码：	e0
长度：	22 mm	内存密度：	37748736 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	72
功能数量：	1	端子数量：	209
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA209,11X19,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.96 mm	最大待机电流：	0.12 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

CY7C1464AV33-200BGI 数据手册

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CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined SRAM with NoBL™ Architecture

Functional Description

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are

3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back

Read/Write operations with no wait states. The

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

CY7C1460AV33/CY7C1462AV33/CY7C1464AV33

are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

Write/Read

transitions.

The

• 3.3V power supply

CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin

compatible and functionally equivalent to ZBT devices.

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

• CY7C1460AV33, CY7C1462AV33 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1464AV33

available in lead-free and non-lead-free 209-ball FBGA

package

Write operations are controlled by the Byte Write Selects

(BW_a–BW_h

CY7C1460AV33 and BW_a–BW_bfor CY7C1462AV33) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

for

CY7C1464AV33,

BW_a–BW_d

for

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram-CY7C1460AV33 (1M x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05353 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2006

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与CY7C1464AV33-200BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1464AV33-200BGXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV33-200BGXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV33-250	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV33-250BGC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV33-250BGI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV33-250BGXC	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464AV33-250BGXI	CYPRESS	获取价格	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
CY7C1464V25	ETC	获取价格	Memory
CY7C1464V25-167BX	CYPRESS	获取价格	ZBT SRAM, 512KX72, 3.5ns, CMOS, PBGA209, 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209
CY7C1464V25-200BX	CYPRESS	获取价格	ZBT SRAM, 512KX72, 3ns, CMOS, PBGA209, 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209

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