Datasheet > CY7C144AV_12

CY7C144AV_12

更新时间： 2022-05-13 19:37:16

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
21页	557K
描述
3.3 V 8 K / 16 K Ã 8 Asynchronous Dual-Port Static RAM

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CY7C144AV_12 数据手册

CY7C144AV

CY7C006AV

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms

3.3 V

= 250 

OUTPUT

30 pF

R1 = 590 

OUTPUT

C = 5 pF

= 1.4 V

C = 30 pF

R2 = 435 

(a) Normal Load (Load 1)

(b) Thévenin Equivalent (Load 1)

ALL INPUTPULSES

(Used for t_LZ, t_HZ, t_HZWE& t_LZWE

3.0V

GND

including scope and jig)

90%

10%

3 ns

10%

3 ns



Data Retention Mode

Timing

The CY7C144AV and CY7C006AV are designed with battery

backup in mind. Data retention voltage and supply current are

guaranteed over temperature. The following rules ensure data

retention:

Figure 4. Timing

Data Retention Mode

3.0 V

1. Chip enable (CE) must be held HIGH during data retention,

within V_CCto V_CC– 0.2 V.

3.0 V

2.0 V

2. CE must be kept between V_CC– 0.2 V and 70% of V_CCduring

the power-up and power-down transitions.

to V – 0.2 V

3. The RAM can begin operation > t_RCafter V_CCreaches the

minimum operating voltage (3.0 Volts).

Parameter

Test Conditions ^[8]

@ VCC_DR= 2 V

Max

Unit

ICC_DR1

A

Note

8. CE = V , V = GND to V , T = 25 °C. This parameter is guaranteed but not tested.

Document Number: 38-06051 Rev. *H

Page 7 of 21

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