Datasheet > CY7C144AV_12

CY7C144AV_12

更新时间： 2022-05-13 19:37:16

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
21页	557K
描述
3.3 V 8 K / 16 K Ã 8 Asynchronous Dual-Port Static RAM

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CY7C144AV_12 数据手册

CY7C144AV

CY7C006AV

DC input voltage ^[5]............................. –0.5 V to V_CC+ 0.5 V

Output current into outputs (LOW) ............................. 20 mA

Static discharge voltage ..........................................> 2001 V

Latch-up current ....................................................> 200 mA

Maximum Ratings

Exceeding maximum ratings ^[4]may impair the useful life of the

device. These user guidelines are not tested.

Storage temperature ................................ –65 °C to +150 °C

Ambient temperature with

Power applied .......................................... –55 °C to +125 °C

Operating Range

Supply voltage to ground potential ..............–0.5 V to +4.6 V

Ambient Temperature

Range

V_CC

DC voltage applied to

Outputs in High Z state ........................–0.5 V to V_CC+ 0.5 V

Commercial

0 °C to +70 °C

3.3 V  300 mV

Electrical Characteristics

Over the Operating Range

CY7C144AV/CY7C006AV

Parameter

Description

-25

Typ

–

Unit

Min

2.4

–

Max

–

V_OH

Output HIGH voltage (V_CC= 3.3 V)

V_OL

V_IH

V_IL

Output LOW voltage

Input HIGH voltage

Input LOW voltage

Output leakage current

0.4

–

2.0

–

0.8

I_OZ

I_CC

–10

–

A

Operating current (V_CC= Max., I_OUT= 0 mA)

Outputs Disabled

Commercial

115

165

I_SB1

I_SB2

I_SB3

I_SB4

Standby current (Both ports TTL level)

Commercial

–

A

[6]

CE_L& CE_R V_IH, f = f_MAX

Standby current (One port TTL level)

[6]

CE_L| CE_R V_IH, f = f_MAX

Standby current (Both ports CMOS level)

500

CE_L& CE_R V_CC– 0.2 V, f = 0 ^[6]

Standby current (One port CMOS level)

[6]

CE_L| CE_R V_IH, f = f_MAX

Capacitance

Parameter ^[7]

Description

Test Conditions

Max

Unit

C_IN

Input capacitance

T_A= 25 °C, f = 1 MHz, V_CC= 3.3 V

C_OUT

Output capacitance

Notes

4. The Voltage on any input or I/O pin can not exceed the power pin during power-up.

5. Pulse width < 20 ns.

= 1/t . All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I

MAX

SB3

7. Tested initially and after any design or process changes that may affect these parameters.

Document Number: 38-06051 Rev. *H

Page 6 of 21

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